公开(公告)号：US08629028B2

公开(公告)日：2014-01-14

申请号：US13773881

申请日：2013-02-22

Applicant: International Business Machines Corporation

Inventor： Christopher V. Baiocco ,  Daniel J. Jaeger ,  Carl J. Radens ,  Helen Wang

IPC: H01L21/336

CPC classification number: H01L29/7816 ,  H01L21/28247 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/78

Abstract: A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.

公开(公告)号：US20130337624A1

公开(公告)日：2013-12-19

申请号：US13773881

申请日：2013-02-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christopher V. Baiocco ,  Daniel J. Jaeger ,  Carl J. Radens ,  Helen Wang

IPC: H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/28247 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/78

Abstract: A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.

公开(公告)号：US09034748B2

公开(公告)日：2015-05-19

申请号：US14017918

申请日：2013-09-04

Applicant: International Business Machines Corporation

Inventor： Christopher V. Baiocco ,  Kevin K. Chan ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Fei Liu ,  Dae-Gyu Park ,  Helen Wang ,  Xinhui Wang ,  Min Yang

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/28 ,  H01L29/66 ,  H01L21/033 ,  H01L21/3213

CPC classification number: H01L21/28132 ,  H01L21/0332 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/6681 ,  Y10S438/95

Abstract: Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.

Abstract translation: 实施例包括一种方法，包括在第一层上沉积硬掩模层，硬掩模层包括： 下硬掩模层，硬掩模停止层和上硬掩模。 图案化硬掩模层和第一层，并且沉积在图案化侧壁上的间隔物。 通过相对于硬掩模阻挡层的选择性蚀刻去除上部硬掩模层和间隔物的顶部，剩余的间隔物材料延伸到侧壁上的第一预定位置。 通过相对于下部硬掩模层和间隔物的选择性蚀刻除去硬掩模阻挡层。 通过相对于第一层选择性地蚀刻下部硬掩模层和间隔物来去除间隔物的第一硬掩模层和顶部，剩余的间隔物材料延伸到侧壁上的第二预定位置。

公开(公告)号：US20130181267A1

公开(公告)日：2013-07-18

申请号：US13788776

申请日：2013-03-07

Applicant: International Business Machines Corporation

Inventor： Martin Burkhardt ,  Matthew E. Colburn ,  Allen H. Gabor ,  Oleg Glushcenkov ,  Scott D. Halle ,  Howard S. Landis ,  Helen Wang

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/28123 ,  H01L21/32139 ,  H01L22/12 ,  H01L22/26

Abstract: A semiconductor device includes an active region including an element formed in a double etch, double exposure method and an inactive region including one or more fills, at least one of the one or more fills including a cut-away hole formed therein, where the cut-away holes expose a layer in the inactive region used for an endpoint detection.

Abstract translation: 半导体器件包括有源区，包括以双蚀刻形成的元件，双曝光方法和包括一个或多个填充物的非活性区域，所述一个或多个填充物中的至少一个填充物包括形成在其中的切除孔， 未使用的孔暴露用于端点检测的非活动区域中的层。

公开(公告)号：US20150064897A1

公开(公告)日：2015-03-05

申请号：US14017918

申请日：2013-09-04

Applicant: International Business Machines Corporation

Inventor： Christopher V. Baiocco ,  Kevin K. Chan ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Fei Liu ,  Dae-Gyu Park ,  Helen Wang ,  Xinhui Wang ,  Min Yang

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28132 ,  H01L21/0332 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/6681 ,  Y10S438/95

Abstract: Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.

Abstract translation: 实施例包括一种方法，包括在第一层上沉积硬掩模层，硬掩模层包括： 下硬掩模层，硬掩模停止层和上硬掩模。 图案化硬掩模层和第一层，并且沉积在图案化侧壁上的间隔物。 通过相对于硬掩模阻挡层的选择性蚀刻去除上部硬掩模层和间隔物的顶部，剩余的间隔物材料延伸到侧壁上的第一预定位置。 通过相对于下部硬掩模层和间隔物的选择性蚀刻除去硬掩模阻挡层。 通过相对于第一层选择性地蚀刻下部硬掩模层和间隔物来去除间隔物的第一硬掩模层和顶部，剩余的间隔物材料延伸到侧壁上的第二预定位置。