公开(公告)号：US11437083B2

公开(公告)日：2022-09-06

申请号：US17168891

申请日：2021-02-05

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Eric Raymond Evarts

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: A magnetoresistive random-access memory (MRAM) device includes a first cell selectively connected to a first bit line and a second cell selectively connected to a second bit line. The MRAM device further includes a shared transistor connected to the first cell and connected to the second cell. The MRAM device further includes a first selector device and a second selector device. The first selector device is configured to permit current to flow through the first cell to the shared transistor when a voltage applied to the first selector device is larger than a threshold activation voltage. The second selector device is configured to permit current to flow through the second cell to the shared transistor when a voltage applied to the second selector device is larger than a threshold activation voltage. The MRAM cell further includes a word line connected to a gate of the shared transistor.

公开(公告)号：US20210158850A1

公开(公告)日：2021-05-27

申请号：US16693469

申请日：2019-11-25

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Eric Raymond Evarts ,  Virat Vasav Mehta ,  Bahman Hekmatshoartabari

IPC: G11C11/16 ,  H01L27/22 ,  H01S5/183 ,  H01S5/343 ,  H01L43/02 ,  H01L43/12 ,  H01F41/34 ,  H01S5/026 ,  H01L23/00

Abstract: An erasable magnetoresistive random-access memory (MRAM) structure and a method of making the same includes an MRAM cell disposed between bit line and word line circuit elements, and a vertical-cavity surface-emitting laser (VCSEL) element disposed above the MRAM cell. A laser output of the VCSEL is directed toward the MRAM cell.

公开(公告)号：US10727273B2

公开(公告)日：2020-07-28

申请号：US16159798

申请日：2018-10-15

Applicant: International Business Machines Corporation

Inventor： Praveen Joseph ,  Xuefeng Liu ,  Gauri Karve ,  Eric Raymond Evarts

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A MRAM-TFT unit cell and a method for fabricating the same. The MRAM-TFT unit cell includes a MRAM device and a TFT device electrically coupled to the MRAM device. The MRAM device and the TFT device are situated within a common plane of the MRAM-TFT cell. The method includes forming a TFT device comprising a source/drain region, and a semiconducting layer on a substrate. A magnetic tunnel junction stack (MTJ) is formed in contact with the source region. A first contact is formed on the MTJ, and a second contact is formed on the drain region. A first interconnect metal layer is formed in contact with the first contact, and a second first interconnect metal layer is formed in contact with the second contact. A third contact is formed on a gate region of the TFT device. A third interconnect metal layer is formed in contact with the third contact.

公开(公告)号：US20200217735A1

公开(公告)日：2020-07-09

申请号：US16241543

申请日：2019-01-07

Applicant: International Business Machines Corporation

Inventor： Virat Vasav Mehta ,  Alexander Reznicek ,  Chandrasekharan Kothandaraman ,  Eric Raymond Evarts ,  Pouya Hashemi

IPC: G01L9/16 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02

Abstract: A sub-micrometer pressure sensor is provided that includes a multilayered magnetic tunnel junction (MTJ) pillar that contains a non-magnetic metallic spacer separating a first magnetic free layer from a second magnetic free layer. The presence of the non-magnetic metallic spacer in the multilayered MTJ pillar improves the sensitivity without compromising area, and makes the pressure sensor binary (either “on” or “off”) with little or no drift, and sensitivity change over time. Moreover, the resistivity switch in such a pressure sensor is instantly and a low error rate is observed.

公开(公告)号：US11942126B2

公开(公告)日：2024-03-26

申请号：US17331008

申请日：2021-05-26

Applicant: International Business Machines Corporation

Inventor： Michael Rizzolo ,  Saba Zare ,  Virat Vasav Mehta ,  Eric Raymond Evarts

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a top contact, a hard mask layer below the top contact, and a magnetic tunnel junction (MTJ) below the hard mask layer. The MRAM cell further comprises a diffusion barrier below the MTJ, a bottom contact below the diffusion barrier, and a magnetic liner arranged around the bottom contact.

公开(公告)号：US11665974B2

公开(公告)日：2023-05-30

申请号：US17248479

申请日：2021-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael Rizzolo ,  Saba Zare ,  Virat Vasav Mehta ,  Eric Raymond Evarts

IPC: G11C11/00 ,  G11C11/16

CPC classification number: H10N50/10 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: An embodiment of the invention may include a magnetic random-access memory (MRAM) structure and method of making the structure. The MRAM structure may include a magnetic tunnel junction stack. The MRAM structure may include a magnetic liner located between the magnetic tunnel junction stack and a top contact, where the magnetic liner may be a ferromagnetic material. This may enable the magnetic liner to act as an independent variable to balance many of the magnetic parameters in the MTJ film stack in order to achieve zero magnetic field at the MTJ layer.

公开(公告)号：US20230046923A1

公开(公告)日：2023-02-16

申请号：US17401415

申请日：2021-08-13

Applicant: International Business Machines Corporation

Inventor： Eric Raymond Evarts ,  Virat Vasav Mehta ,  Oscar van der Straten

IPC: H01L27/22 ,  H01L43/06 ,  H01L43/04 ,  G11C11/16 ,  H01L43/14

Abstract: A spin-orbit torque magnetoresistive random-access memory device formed by fabricating a spin-Hall-effect (SHE) layer above and in electrical contact with a transistor, forming a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, a reference layer, and a diode structure, forming a write line disposed in electrical contact with the SHE rail, forming a protective dielectric layer covering a portion of the SOT-MRAM cell stack, and forming a read line disposed above and adjacent to the diode structure.

公开(公告)号：US11114146B2

公开(公告)日：2021-09-07

申请号：US16693469

申请日：2019-11-25

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Eric Raymond Evarts ,  Virat Vasav Mehta ,  Bahman Hekmatshoartabari

IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22 ,  H01S5/183 ,  H01S5/343 ,  H01L43/02 ,  H01F41/34 ,  H01S5/026 ,  H01L23/00 ,  H01L43/12 ,  H01F10/32 ,  H01L43/10

Abstract: An erasable magnetoresistive random-access memory (MRAM) structure and a method of making the same includes an MRAM cell disposed between bit line and word line circuit elements, and a vertical-cavity surface-emitting laser (VCSEL) element disposed above the MRAM cell. A laser output of the VCSEL is directed toward the MRAM cell.

公开(公告)号：US12153821B2

公开(公告)日：2024-11-26

申请号：US17809184

申请日：2022-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Krishna Thangaraj ,  Heng Wu ,  Eric Raymond Evarts

IPC: G06F3/06 ,  G06F12/0802

Abstract: A memory system for storage access monitoring is provided. The memory system includes a media controller of a memory. An analog persistent circuit is coupled to the media controller and configured to monitor access to the memory. The analog persistent circuit stores persistent data related to memory access counts access signals from the command/address bus. A command/address bus is coupled to the analog persistent circuit. A memory array is communicatively coupled to the command address and the media controller.

公开(公告)号：US20240304261A1

公开(公告)日：2024-09-12

申请号：US18179478

申请日：2023-03-07

Applicant: International Business Machines Corporation

Inventor： Krishna Thangaraj ,  Eric Raymond Evarts

IPC: G11C16/34

CPC classification number: G11C16/3404

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a flash controller and a first flash chip communicably coupled with the flash controller. The first flash chip may include a first flash cell array and a first voltage recalibration analog circuit (VRAC) configured to adjust a first threshold voltage for the first flash cell array based on a tracking of accesses to the first flash cell array.