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    3D-microstrip branchline coupler
    1.
    发明授权
    3D-microstrip branchline coupler 有权

    公开(公告)号：US10832989B2

    公开(公告)日：2020-11-10

    申请号：US16583987

    申请日：2019-09-26

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Barbara S. DeWitt ,  Essam Mina ,  B M Farid Rahman ,  Guoan Wang

    IPC: H01P5/18 ,  H01L23/48 ,  H01P3/08 ,  H01P11/00 ,  H01P3/00 ,  H01P3/02 ,  G06F30/394 ,  H01Q1/22 ,  H01Q13/10

    Abstract: The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.

    High performance on-chip vertical coaxial cable, method of manufacture and design structure
    4.
    发明授权
    High performance on-chip vertical coaxial cable, method of manufacture and design structure 有权
    高性能片上垂直同轴电缆，制造方法和设计结构

    公开(公告)号：US09054157B2

    公开(公告)日：2015-06-09

    申请号：US14076656

    申请日：2013-11-11

    Applicant: International Business Machines Corporation

    Inventor： Essam Mina ,  Guoan Wang ,  Wayne H. Woods, Jr.

    IPC: H01L21/768 ,  H01L23/498 ,  G06F17/50

    CPC classification number: H01L21/768 ,  G06F17/505 ,  H01L23/49827 ,  H01L2924/0002 ,  Y10T29/49123 ,  H01L2924/00

    Abstract: A high performance on-chip vertical coaxial cable structure, method of manufacturing and design structure thereof is provided. The coaxial cable structure includes an inner conductor and an insulating material that coaxially surrounds the inner conductor. The structure further includes an outer conductor which surrounds the insulating material. Both the inner and outer conductors comprise a plurality of metal layers formed on different wiring levels and interconnected between the different wiring levels by conductors. The coaxial cable structure is formed upon a surface of a semiconductor substrate and is oriented in substantially perpendicular alignment with the surface.

    Abstract translation: 提供了一种高性能的片上垂直同轴电缆结构，其制造方法和设计结构。 同轴电缆结构包括同轴地围绕内导体的内导体和绝缘材料。 该结构还包括围绕绝缘材料的外导体。 内导体和外导体都包括形成在不同布线层上的多个金属层，并且通过导体在不同布线层之间互连。 同轴电缆结构形成在半导体衬底的表面上并且与表面基本上垂直对齐。

    Methodology on developing metal fill as library device
    5.
    发明授权
    Methodology on developing metal fill as library device 有权
    开发金属填充作为库设备的方法

    公开(公告)号：US08930871B2

    公开(公告)日：2015-01-06

    申请号：US14068524

    申请日：2013-10-31

    Applicant: International Business Machines Corporation

    Inventor： Essam Mina ,  Guoan Wang

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A methodology for developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure is disclosed. The method is implemented on a computing device and includes generating a model for effects of metal fill in an integrated circuit. The metal fill model is generated prior to completion of a layout design for the integrated circuit.

    Abstract translation: 公开了一种用于开发金属填充作为库装置的方法，特别是一种产生集成电路中的金属填充物的效果（例如电容）的模型和设计结构的方法。 该方法在计算设备上实现，并且包括生成用于集成电路中的金属填充效应的模型。 金属填充模型在完成集成电路的布局设计之前生成。

    HIGH PERFORMANCE ON-CHIP VERTICAL COAXIAL CABLE, METHOD OF MANUFACTURE AND DESIGN STRUCTURE
    6.
    发明申请
    HIGH PERFORMANCE ON-CHIP VERTICAL COAXIAL CABLE, METHOD OF MANUFACTURE AND DESIGN STRUCTURE 有权
    高性能片上垂直同轴电缆，制造方法和设计结构

    公开(公告)号：US20140065817A1

    公开(公告)日：2014-03-06

    申请号：US14076656

    申请日：2013-11-11

    Applicant: International Business Machines Corporation

    Inventor： Essam Mina ,  Guoan Wang ,  Wayne H. Woods, JR.

    IPC: H01L21/768 ,  G06F17/50

    CPC classification number: H01L21/768 ,  G06F17/505 ,  H01L23/49827 ,  H01L2924/0002 ,  Y10T29/49123 ,  H01L2924/00

    Abstract: A high performance on-chip vertical coaxial cable structure, method of manufacturing and design structure thereof is provided. The coaxial cable structure includes an inner conductor and an insulating material that coaxially surrounds the inner conductor. The structure further includes an outer conductor which surrounds the insulating material. Both the inner and outer conductors comprise a plurality of metal layers formed on different wiring levels and interconnected between the different wiring levels by conductors. The coaxial cable structure is formed upon a surface of a semiconductor substrate and is oriented in substantially perpendicular alignment with the surface.

    Abstract translation: 提供了一种高性能的片上垂直同轴电缆结构，其制造方法和设计结构。 同轴电缆结构包括同轴地围绕内导体的内导体和绝缘材料。 该结构还包括围绕绝缘材料的外导体。 内导体和外导体都包括形成在不同布线层上的多个金属层，并且通过导体在不同布线层之间互连。 同轴电缆结构形成在半导体衬底的表面上并且与表面基本上垂直对齐。

    3D-microstrip branchline coupler
    8.
    发明授权
    3D-microstrip branchline coupler 有权

    公开(公告)号：US10586752B2

    公开(公告)日：2020-03-10

    申请号：US15997837

    申请日：2018-06-05

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Barbara S. DeWitt ,  Essam Mina ,  B M Farid Rahman ,  Guoan Wang

    IPC: H01P5/18 ,  H01P5/22 ,  H01L23/48 ,  H01P3/08 ,  H01P11/00 ,  H01P3/00 ,  H01P3/02 ,  G06F17/50 ,  H01Q1/22 ,  H01Q13/10

    Abstract: The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.

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