公开(公告)号：US20170365713A1

公开(公告)日：2017-12-21

申请号：US15422724

申请日：2017-02-02

Applicant: International Business Machines Corporation

Inventor： KANGGUO CHENG ,  JUNTAO LI ,  GENG WANG ,  QINTAO ZHANG

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/311 ,  H01L21/265 ,  H01L21/223 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7827 ,  H01L21/0228 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/31116 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66666

Abstract: A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure that includes a fin on a semiconductor substrate, forming a source junction or a drain junction at an upper surface of the semiconductor substrate and at a base of the fin and epitaxially growing a rare earth oxide (REO) spacer to have a substantially uniform thickness along respective upper surfaces of the source or drain junction and on opposite sides of the fin structure.

公开(公告)号：US20180090605A1

公开(公告)日：2018-03-29

申请号：US15607796

申请日：2017-05-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KANGGUO CHENG ,  JUNTAO LI ,  GENG WANG ,  QINTAO ZHANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78696

Abstract: A method of manufacturing an integrated circuit is provided. According to the method, a layered fin including a plurality of sacrificial layers and semiconductor layers wherein two adjacent semiconductor layers are separated by the sacrificial layer is provided on a semiconductor substrate. A gate over the layered fin and a spacer surrounding a sidewall of the gate are then formed. The sacrificial layers are subsequently removed to provide a structure in which two adjacent semiconductor layers are separated by a gap. The method further includes forming an insulator in the gap and forming source and drain regions located on the layered fin. The insulator includes a high-K dielectric material surrounded by a low-K dielectric material, both of which are in contact with the two adjacent semiconductor layers.

公开(公告)号：US20180053758A1

公开(公告)日：2018-02-22

申请号：US15698041

申请日：2017-09-07

Applicant: International Business Machines Corporation

Inventor： KANGGUO CHENG ,  JUNTAO LI ,  GENG WANG ,  QINTAO ZHANG

IPC: H01L27/06 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/868 ,  H01L29/78 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0255 ,  H01L27/092 ,  H01L29/0657 ,  H01L29/66136 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/868

Abstract: An integrated device is provided. The integrated device includes a substrate having a doped upper surface section and an insulator to define first and second substrate regions on opposite sides thereof. Vertical transistors are operably arranged on the doped upper surface section at the first substrate region. P-I-N diodes are operably arranged on the doped upper surface section at the second substrate region.