公开(公告)号：US20160118348A1

公开(公告)日：2016-04-28

申请号：US14522083

申请日：2014-10-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mukta G. FAROOQ ,  John A. FITZSIMMONS ,  Erdem KALTALIOGLU ,  Wei LIN ,  Spyridon SKORDAS ,  Kevin R. WINSTEL

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/66 ,  H01L23/522 ,  H01L21/302 ,  H01L21/288 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/562 ,  H01L21/2885 ,  H01L21/302 ,  H01L21/76898 ,  H01L22/34 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Strain detection structures used with bonded wafers and chips and methods of manufacture are disclosed. The method includes forming lower metal wiring structures associated with a lower wafer structure. The method further includes bonding the lower wafer structure to an upper wafer structure and thinning the upper wafer, and forming upper metal wiring structures. The method further includes electrically linking the lower metal wiring structures to the upper metal wiring structures by formation of through silicon via structures to form an electrically connected chain extending between multiple wafer structures. The method further includes forming contacts to an outside environment which electrically contact two of the lower metal wiring structures.

Abstract translation: 公开了与键合晶片和芯片一起使用的应变检测结构和制造方法。 该方法包括形成与下晶片结构相关联的下金属布线结构。 该方法还包括将下晶片结构接合到上晶片结构并使上晶片变薄，并形成上金属布线结构。 该方法还包括通过形成穿过硅的结构将下部金属布线结构电连接到上部金属布线结构，以形成在多个晶片结构之间延伸的电连接链。 该方法还包括形成与外部环境的接触，该外部环境电接触两个下部金属布线结构。

公开(公告)号：US20140356981A1

公开(公告)日：2014-12-04

申请号：US13903198

申请日：2013-05-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alex R. HUBBARD ,  Douglas C. LA TULIPE, JR. ,  Spyridon SKORDAS ,  Kevin R. WINSTEL

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/12 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/08145 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/8013 ,  H01L2224/80896 ,  H01L2224/80908 ,  H01L2224/8113 ,  H01L2224/81908 ,  H01L2224/8313 ,  H01L2224/83908 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/3511 ,  H01L2224/80 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014

Abstract: A method for wafer bonding includes measuring grid distortion for a mated pairing of wafers to be bonded to determine if misalignment exists between the wafers. During processing of subsequent wafers, magnification of one or more lithographic patterns is adjusted to account for the misalignment. The subsequent wafers are bonded with reduced misalignment.

Abstract translation: 用于晶片接合的方法包括测量待接合的晶片的配对配对的栅格畸变，以确定晶片之间是否存在偏差。 在后续晶片的处理期间，调整一个或多个光刻图案的放大率以解决未对准。 随后的晶片以缩小的未对准结合。

公开(公告)号：US20160343564A1

公开(公告)日：2016-11-24

申请号：US14718747

申请日：2015-05-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Richard F. INDYK ,  Deepika PRIYADARSHINI ,  Spyridon SKORDAS ,  Edmund J. SPROGIS ,  Anthony K. STAMPER ,  Kevin R. WINSTEL

IPC: H01L21/02 ,  B32B7/12 ,  B32B3/30 ,  H01L21/683 ,  B32B3/02

CPC classification number: H01L21/02035 ,  B32B3/02 ,  B32B3/26 ,  B32B3/30 ,  B32B7/12 ,  B32B9/04 ,  B32B9/045 ,  B32B27/06 ,  B32B2250/02 ,  B32B2250/44 ,  B32B2255/20 ,  B32B2255/26 ,  B32B2457/14 ,  H01L21/02013 ,  H01L21/02021

Abstract: Edge trim processes in 3D integrated circuits and resultant structures are provided. The method includes trimming an edge of a wafer at an angle to form a sloped sidewall. The method further includes attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer. The method further includes thinning the wafer while it is attached to the wafer.

Abstract translation: 提供3D集成电路和结构结构中的边缘修剪工艺。 该方法包括以一定角度修剪晶片的边缘以形成倾斜侧壁。 该方法还包括将晶片附接到具有接合到载体晶片的晶片的较小直径下部的载体晶片。 该方法还包括在晶片附着到晶片时使晶片变薄。