公开(公告)号：US20190326289A1

公开(公告)日：2019-10-24

申请号：US16460018

申请日：2019-07-02

Applicant: International Business Machines Corporation

Inventor： Lawrence A. CLEVENGER ,  Leigh Anne H. CLEVENGER ,  Mona A. EBRISH ,  Gauri KARVE ,  Fee Li LIE ,  Deepika PRIYADARSHINI ,  Indira Priyavarshini SESHADRI ,  Nicole A. SAULNIER

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/161 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L29/10

Abstract: A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.

公开(公告)号：US20160329279A1

公开(公告)日：2016-11-10

申请号：US15214760

申请日：2016-07-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel C. EDELSTEIN ,  Son V. NGUYEN ,  Takeshi NOGAMI ,  Deepika PRIYADARSHINI ,  Hosadurga K. SHOBHA

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/02068 ,  H01L21/02172 ,  H01L21/02244 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

公开(公告)号：US20160056112A1

公开(公告)日：2016-02-25

申请号：US14882568

申请日：2015-10-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel C. EDELSTEIN ,  Son V. NGUYEN ,  Takeshi NOGAMI ,  Deepika PRIYADARSHINI ,  Hosadurga K. SHOBHA

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76879 ,  H01L21/02068 ,  H01L21/02172 ,  H01L21/02244 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Abstract translation: 公开了低电容和高可靠性互连结构和制造方法。 该方法包括在电介质材料的开口中形成铜基互连结构。 该方法还包括在铜基互连结构上形成覆盖层。 该方法还包括氧化覆盖层和形成在电介质材料的表面上的任何残留材料。 该方法还包括通过从铜基互连结构向包覆层的表面外扩散材料，在封盖层上形成阻挡层。 该方法还包括去除残留材料，同时覆盖层表面上的阻挡层保护覆盖层。

公开(公告)号：US20160343564A1

公开(公告)日：2016-11-24

申请号：US14718747

申请日：2015-05-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Richard F. INDYK ,  Deepika PRIYADARSHINI ,  Spyridon SKORDAS ,  Edmund J. SPROGIS ,  Anthony K. STAMPER ,  Kevin R. WINSTEL

IPC: H01L21/02 ,  B32B7/12 ,  B32B3/30 ,  H01L21/683 ,  B32B3/02

CPC classification number: H01L21/02035 ,  B32B3/02 ,  B32B3/26 ,  B32B3/30 ,  B32B7/12 ,  B32B9/04 ,  B32B9/045 ,  B32B27/06 ,  B32B2250/02 ,  B32B2250/44 ,  B32B2255/20 ,  B32B2255/26 ,  B32B2457/14 ,  H01L21/02013 ,  H01L21/02021

Abstract: Edge trim processes in 3D integrated circuits and resultant structures are provided. The method includes trimming an edge of a wafer at an angle to form a sloped sidewall. The method further includes attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer. The method further includes thinning the wafer while it is attached to the wafer.

Abstract translation: 提供3D集成电路和结构结构中的边缘修剪工艺。 该方法包括以一定角度修剪晶片的边缘以形成倾斜侧壁。 该方法还包括将晶片附接到具有接合到载体晶片的晶片的较小直径下部的载体晶片。 该方法还包括在晶片附着到晶片时使晶片变薄。

公开(公告)号：US20160056076A1

公开(公告)日：2016-02-25

申请号：US14466539

申请日：2014-08-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel C. EDELSTEIN ,  Son V. NGUYEN ,  Takeshi NOGAMI ,  Deepika PRIYADARSHINI ,  Hosadurga K. SHOBHA

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/02068 ,  H01L21/02172 ,  H01L21/02244 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

公开(公告)号：US20180090371A1

公开(公告)日：2018-03-29

申请号：US15825646

申请日：2017-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel C. EDELSTEIN ,  Son V. NGUYEN ,  Takeshi NOGAMI ,  Deepika PRIYADARSHINI ,  Hosadurga K. SHOBHA

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/76879 ,  H01L21/02068 ,  H01L21/02172 ,  H01L21/02244 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

公开(公告)号：US20170140981A1

公开(公告)日：2017-05-18

申请号：US15417390

申请日：2017-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel C. EDELSTEIN ,  Son V. NGUYEN ,  Takeshi NOGAMI ,  Deepika PRIYADARSHINI ,  Hosadurga K. SHOBHA

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/76879 ,  H01L21/02068 ,  H01L21/02172 ,  H01L21/02244 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

公开(公告)号：US20200051854A1

公开(公告)日：2020-02-13

申请号：US16657169

申请日：2019-10-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel C. EDELSTEIN ,  Son V. NGUYEN ,  Takeshi NOGAMI ,  Deepika PRIYADARSHINI ,  Hosadurga K. SHOBHA

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

公开(公告)号：US20180374748A1

公开(公告)日：2018-12-27

申请号：US16118998

申请日：2018-08-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel C. EDELSTEIN ,  Son V. NGUYEN ,  Takeshi NOGAMI ,  Deepika PRIYADARSHINI ,  Hosadurga K. SHOBHA

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76879 ,  H01L21/02068 ,  H01L21/02172 ,  H01L21/02244 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

公开(公告)号：US20180197858A1

公开(公告)日：2018-07-12

申请号：US15402704

申请日：2017-01-10

Applicant: International Business Machines Corporation

Inventor： Lawrence A. CLEVENGER ,  Leigh Anne H. CLEVENGER ,  Mona A. EBRISH ,  Gauri KARVE ,  Fee Li LIE ,  Deepika PRIYADARSHINI ,  Indira Priyavarshini SESHADRI ,  Nicole A. SAULNIER

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/8258 ,  H01L21/027 ,  H01L21/311 ,  H01L21/033 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/7849

Abstract: A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.