公开(公告)号：US20200027840A1

公开(公告)日：2020-01-23

申请号：US16039570

申请日：2018-07-19

Applicant: International Business Machines Corporation

Inventor： Benjamin D. BRIGGS ,  Cornelius Brown PEETHALA ,  Michael RIZZOLO ,  Koichi MOTOYAMA ,  Gen TSUTSUI ,  Ruqiang BAO ,  Gangadhara Raja MUTHINTI ,  Lawrence A. CLEVENGER

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L21/306 ,  H01L21/48

Abstract: A method for fabricating semiconductor wafers comprises creating a semiconductor wafer having a plurality of wide copper wires and a plurality of narrow copper wires embedded in a dielectric insulator. The width of each wide copper wire is greater than a cutoff value and each narrow copper is less than the cutoff value. An optical pass through layer is deposited over a top surface of the wafer and a photo-resist layer is deposited over the optical pass through layer. The wafer is exposed to a light source to selectively remove photo-resist, forming a self-aligned pattern where photo-resist only remains in areas above wide copper wires. The self-aligned pattern is transferred to the optical pass through layer and the remaining photo-resist is removed. The wafer is chemically etched to remove the narrow copper wires, defining narrow gaps in the dielectric insulator. The wafer is metallized with non-copper metal, forming narrow non-copper metal wires.

公开(公告)号：US20180366408A1

公开(公告)日：2018-12-20

申请号：US16049442

申请日：2018-07-30

Applicant: International Business Machines Corporation

Inventor： Benjamin David BRIGGS ,  Lawrence A. CLEVENGER ,  Bartlef H. DEPROSPO ,  Huai HUANG ,  Christopher J. PENNY ,  Michael RIZZOLO

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2221/1047

Abstract: A method of forming a semiconductor device includes forming a porous dielectric layer including a recessed portion, forming a conductive layer in the recessed portion of the porous dielectric layer, and forming a conformal cap layer on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer.

公开(公告)号：US20190215282A1

公开(公告)日：2019-07-11

申请号：US15865530

申请日：2018-01-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. BRIGGS ,  Lawrence A. CLEVENGER ,  Leigh Anne H. CLEVENGER ,  Christoper J. PENNY ,  Michael RIZZOLO ,  Aldis SIPOLINS

IPC: H04L12/58 ,  G06F17/27 ,  G06F15/18 ,  H04L29/08

Abstract: Context appropriate errors are injected into conversational text generated by conversational agents. The conversational agent creates an imperfect conversational text containing at least one text entry error added to the original conversational text. A confidence level that at least one of context and meaning of the imperfect conversational text is consistent with the context and meaning of the original conversational text is determined, and the imperfect conversational text is communicated to a human recipient if the confidence level is above a pre-defined threshold.

公开(公告)号：US20180254242A1

公开(公告)日：2018-09-06

申请号：US15966236

申请日：2018-04-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. BRIGGS ,  Lawrence A. CLEVENGER ,  Bartlet H. DeProspo ,  Michael RIZZOLO ,  Nicole A. SAULNIER

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53228

Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.

公开(公告)号：US20200006655A1

公开(公告)日：2020-01-02

申请号：US16019798

申请日：2018-06-27

Applicant: International Business Machines Corporation

Inventor： Hao TANG ,  Michael RIZZOLO ,  Injo OK ,  Theodorus E. STANDAERT

IPC: H01L45/00 ,  H01L23/544 ,  H01L27/24

Abstract: An intermediate semiconductor device structure includes a first area including a memory stack area and a second area including an alignment mark area. The intermediate structure includes a metal interconnect arranged on a substrate in the first area and a first electrode layer arranged on the metal interconnect in the first area, and in the second area. The intermediate structure includes an alignment assisting marker arranged in the second area. The intermediate structure includes a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area and on the metal interconnect in the first area. The intermediate structure includes a hard mask layer arranged on the second electrode area. The hard mask layer provides a raised area of topography over the alignment assisting marker. The intermediate structure includes a resist arranged on the hard mask layer in the first area.

公开(公告)号：US20190262941A1

公开(公告)日：2019-08-29

申请号：US16410475

申请日：2019-05-13

Applicant: International Business Machines Corporation

Inventor： Benjamin David BRIGGS ,  Lawrence A. CLEVENGER ,  Bartle H. DEPROSPO ,  Michael RIZZOLO

IPC: B23K26/082 ,  H01L21/66 ,  H01L21/768 ,  B23K26/352 ,  B23K26/062 ,  B23K26/03 ,  B23K26/00 ,  H01L21/67 ,  B23K26/70

Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.

公开(公告)号：US20180366141A1

公开(公告)日：2018-12-20

申请号：US15622577

申请日：2017-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Maryam ASHOORI ,  Benjamin D. BRIGGS ,  Lawrence A. CLEVENGER ,  Leigh Anne H. CLEVENGER ,  Michael RIZZOLO

IPC: G10L25/63 ,  G06F19/00 ,  G10L15/26 ,  A61B5/16

Abstract: Embodiments of the present invention are directed to a computer program product for generating a personality shift determination. The computer program product can include a computer readable storage medium having program instructions embodied therewith, wherein the instructions are executable by a processor to cause the processor to perform a method. The method can include receiving a real-time audio input. The method can also include generating a real-time personality trait identification. The method can also include generating a current trait classification for the real-time personality trait identification. The method can also include comparing the current trait classification to a historic rate classification. The method can also include generating a personality shift determination.

公开(公告)号：US20200075406A1

公开(公告)日：2020-03-05

申请号：US16669708

申请日：2019-10-31

Applicant: international Business Machines Corporation

Inventor： Benjamin David Briggs ,  Lawrence A. CLEVENGER ,  Bartlet H. DEPROSPO ,  Michael RIZZOLO

IPC: H01L21/768 ,  H01L23/532 ,  B23K26/352 ,  B23K26/062 ,  B23K26/70 ,  B23K26/03 ,  B23K26/00 ,  B23K26/082 ,  H01L21/66 ,  H01L21/67

Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.

公开(公告)号：US20180005941A1

公开(公告)日：2018-01-04

申请号：US15199321

申请日：2016-06-30

Applicant: International Business Machines Corporation

Inventor： Benjamin David BRIGGS ,  Lawrence A. CLEVENGER ,  Bartlet H. DEPROSPO ,  Huai HUANG ,  Christopher J. PENNY ,  Michael RIZZOLO

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329

Abstract: A semiconductor device includes a porous dielectric layer formed on an interconnect layer and including a recessed portion, a conductive layer formed in the recessed portion, and a conformal cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer. Porous dielectric material is protected by back-filled pore fillers or leave-in porogens from process integration such as chemical mechanical polishing (CMP). The pore fillers or porogens are removed after CMP and Cap process to achieve low capacitance. A self-aligned cap protects the conductor metal from exposing the severe conditions during the pore filler or porogen removal process.

公开(公告)号：US20200176388A1

公开(公告)日：2020-06-04

申请号：US16782311

申请日：2020-02-05

Applicant: International Business Machines Corporation

Inventor： Benjamin D. BRIGGS ,  Cornelius Brown PEETHALA ,  Michael RIZZOLO ,  Koichi MOTOYAMA ,  Gen TSUTSUI ,  Ruqiang BAO ,  Gangadhara Raja MUTHINTI ,  Lawrence A. CLEVENGER

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/48 ,  H01L21/768 ,  H01L21/306

Abstract: A semiconductor wafer has a top surface, a dielectric insulator, a plurality of narrow copper wires, a plurality of wide copper wires, an optical pass through layer over the top surface, and a self-aligned pattern in a photo-resist layer. The plurality of wide copper wires and the plurality of narrow copper wires are embedded in a dielectric insulator. The width of each wide copper wire is greater than the width of each narrow copper. An optical pass through layer is located over the top surface. A self-aligned pattern in a photo-resist layer, wherein photo-resist exists only in areas above the wide copper wires, is located above the optical pass through layer.