公开(公告)号：US10313122B2

公开(公告)日：2019-06-04

申请号：US15798782

申请日：2017-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kohichi Kamijoh ,  Seiji Munetoh

IPC: H04L9/08

Abstract: Methods for supplying deficiency of a key in a set of keys stored in devices includes receiving information (key values) on the keys from each device. Each key is assigned to a node or pair of nodes in a tree structure(s). If a position of a key in the tree structure in a first set of keys is stored in a first device with its value and corresponds to a position of a key in the tree structure in a second set of keys stored in a second device with its value, the first device and the second device are grouped together. Where there is a missing key in the first set of keys, a key corresponding to the missing key from the second set of keys is found, or a key common in the first set of keys and the second set of keys is found.

公开(公告)号：US10291404B2

公开(公告)日：2019-05-14

申请号：US15453017

申请日：2017-03-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kohichi Kamijoh ,  Seiji Munetoh

IPC: H04L9/08

Abstract: Methods for supplying deficiency of a key in a set of keys stored in devices includes receiving information (key values) on the keys from each device. Each key is assigned to a node or pair of nodes in a tree structure(s). If a position of a key in the tree structure in a first set of keys is stored in a first device with its value and corresponds to a position of a key in the tree structure in a second set of keys stored in a second device with its value, the first device and the second device are grouped together. Where there is a missing key in the first set of keys, a key corresponding to the missing key from the second set of keys is found, or a key common in the first set of keys and the second set of keys is found.

公开(公告)号：US20190139840A1

公开(公告)日：2019-05-09

申请号：US16234852

申请日：2018-12-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Akihiro Horibe ,  Yasuteru Kohda ,  Seiji Munetoh ,  Chitra Subramanian ,  Kuniaki Sueoka

IPC: H01L21/66 ,  H01L21/77

Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.

公开(公告)号：US20180262333A1

公开(公告)日：2018-09-13

申请号：US15798782

申请日：2017-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kohichi Kamijoh ,  Seiji Munetoh

IPC: H04L9/08

CPC classification number: H04L9/0894 ,  H04L9/083

Abstract: Methods for supplying deficiency of a key in a set of keys stored in devices includes receiving information (key values) on the keys from each device. Each key is assigned to a node or pair of nodes in a tree structure(s). If a position of a key in the tree structure in a first set of keys is stored in a first device with its value and corresponds to a position of a key in the tree structure in a second set of keys stored in a second device with its value, the first device and the second device are grouped together. Where there is a missing key in the first set of keys, a key corresponding to the missing key from the second set of keys is found, or a key common in the first set of keys and the second set of keys is found.

公开(公告)号：US09891854B2

公开(公告)日：2018-02-13

申请号：US15349391

申请日：2016-11-11

Applicant: International Business Machines Corporation

Inventor： Seiji Munetoh ,  Nobuyuki Ohba

IPC: G06F12/06 ,  G06F3/06 ,  G06F12/02 ,  G06F9/44 ,  G11C11/4096 ,  G11C14/00

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0685 ,  G06F9/4406 ,  G06F12/0246 ,  G06F12/0638 ,  G06F2212/205 ,  G06F2212/7201 ,  G11C11/4096 ,  G11C14/0009

Abstract: A method for managing main memory including DRAM and NVRAM in a computer depending on the operation state of the computer is provided. The method includes: (a) upon start of the computer, loading a program and the like into the DRAM, and loading predetermined read-only data and the like into the NVRAM; (b) in a state transition from a normal operation to a suspend state, moving data in the DRAM to the NVRAM; (c) in a state transition from the suspend state to the normal operation, reading data from the NVRAM for program execution; (d) in the case where a data write to the NVRAM occurs, stopping the data write, and moving data in a data area of the NVRAM subjected to the data write, to the DRAM; and (e) performing the data write to the DRAM to which the data has been moved.

公开(公告)号：US20170262634A1

公开(公告)日：2017-09-14

申请号：US15607892

申请日：2017-05-30

Applicant: International Business Machines Corporation

Inventor： Seiji Munetoh

IPC: G06F21/56 ,  G06F21/55

CPC classification number: G06F21/566 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/3037 ,  G06F11/3466 ,  G06F11/3476 ,  G06F11/3495 ,  G06F12/145 ,  G06F21/55 ,  G06F21/552 ,  G06F21/554 ,  G06F2212/1016 ,  G06F2212/152

Abstract: Analysis system, analysis method and program. The system includes: trace means for acquiring a command issued by software executed in an information processing system and a physical address of a memory used by the command as trace data, and recording the trace data to storage means; event detecting means for detecting an event caused to occur by the software and acquiring event information; conversion means for converting the event information to a memory access pattern configured with a plurality of commands for accessing the memory and a plurality of physical addresses; and memory accessing means for accessing the memory using the converted memory access pattern, causing the trace means to acquire trace data and record the trace data to the storage means.

公开(公告)号：US20140071785A1

公开(公告)日：2014-03-13

申请号：US14013348

申请日：2013-08-29

Applicant: International Business Machines Corporation

Inventor： Yasunao Katayama ,  Seiji Munetoh ,  Nobuyuki Ohba ,  Tadayuki Okada ,  Atsuya Okazaki

IPC: G11C8/18

CPC classification number: G11C8/18 ,  G06F11/073 ,  G06F11/076 ,  G06F11/30 ,  G06F11/3037 ,  G06F11/3075 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: A method of monitoring signals is disclosed, wherein a plurality of command signals and address signals are consecutively expressed, as a measurement target. The method includes setting a strobe timing that has a predetermined initial value; calculating an error rate by monitoring the plurality of command signals, in accordance with the strobe timing; monitoring the plurality of address signals, and calculating a burst rate from a difference between the consecutive plurality of address signals, in accordance with the strobe timing; identifying timing where the calculated error rate and calculated burst rate are both optimized; and in the event the timing where both the calculated error rate and calculated burst rate are optimized cannot be identified, altering a predetermined value of the set strobe timing, and repeating the calculating, monitoring, and identifying.

Abstract translation: 公开了一种监视信号的方法，其中连续地表示多个命令信号和地址信号作为测量对象。 该方法包括设置具有预定初始值的选通定时; 通过根据所述选通定时监视所述多个命令信号来计算出错率; 监视所述多个地址信号，以及根据所述选通定时从连续多个地址信号之间的差计算突发速率; 识别所计算的错误率和计算的突发速率都被优化的定时; 并且在计算出的错误率和计算的突发速率都被优化的时刻不能被识别，改变设定的选通定时的预定值，并且重复计算，监视和识别。

公开(公告)号：US12148682B2

公开(公告)日：2024-11-19

申请号：US17551457

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： Biswanath Senapati ,  Seiji Munetoh ,  Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  Geoffrey Burr ,  Kohji Hosokawa

IPC: G11C13/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H10B63/00

Abstract: A memory cell in a backside of a wafer and methods of forming the memory cell are described. A buried metal structure can be formed through a frontside of a substrate. At least one device can be formed on the frontside of a substrate, where the at least one device can be connected to the buried metal structure in the substrate. A through silicon via (TSV) can be formed through a backside of the substrate, where the TSV can be connected to the buried metal structure. A memory cell can be formed on the backside of the substrate, where the memory cell can be connected to the TSV.

公开(公告)号：US11190362B2

公开(公告)日：2021-11-30

申请号：US16239255

申请日：2019-01-03

Applicant: International Business Machines Corporation

Inventor： Chitra Subramanian ,  Seiji Munetoh ,  Frank Robert Libsch ,  Daniel Joseph Friedman ,  Ghavam G. Shahidi ,  Arun Paidimarri

IPC: H04L9/32 ,  H04L9/30 ,  G06K19/07 ,  G06K19/077

Abstract: Devices, computer-implemented methods, and systems that can facilitate radio frequency identification components are provided. According to an embodiment, a device can comprise a memory that can be coupled to an integrated circuit device that can have a processor and an accelerator component that can execute a cryptographic module. The device can further comprise a radio frequency identification device that can be coupled to the integrated circuit device that can communicate with a radio frequency identification reader device based on the cryptographic module.

公开(公告)号：US20210240652A1

公开(公告)日：2021-08-05

申请号：US16777786

申请日：2020-01-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Seiji Munetoh

IPC: G06F13/40 ,  G06F13/24

Abstract: An apparatus for data transfer includes a first node connected to a bus to communicate bidirectionally, and second nodes connected in series to the bus. Each second node lacks an internal clock and has fixed pads including a power, a ground, and signal pads to transfer a data frame, return data pads for a return signal, select pads for a selection signal and clock pads for a clock signal. Each second node is indexed by a hop count in the frame that is incremented each time the frame is transferred in topological order. Each second node is selectable using a mode defined by a combination of the hop count, a mask field and an address field in the frame. The signal pads are used for frame transfer in a selected mode controlled by a combination of the selection, clock and return signals.