公开(公告)号：US11782836B1

公开(公告)日：2023-10-10

申请号：US17657169

申请日：2022-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jason D Kohl ,  Winston Herring ,  Tu-An T. Nguyen ,  Gregory William Alexander ,  Timothy Bronson ,  Christian Jacobi

IPC: G06F12/084 ,  G06F9/38 ,  G06F12/0815

CPC classification number: G06F12/084 ,  G06F9/3834 ,  G06F12/0815

Abstract: A primary controller has authority of a cache line associated with a fetch and manages a second cache line request from a different and non-associated secondary requesting entity. A secondary controller, associated with the secondary requesting entity, is granted authority of the cache line and further manages multiple subsequent simultaneous or overlapping requests for the cache line from different non-associated subsequent requesting entities by maintaining authority of the cache line, by granting read-only access to the cache line to respective subsequent controllers, each associated with a different subsequent requesting entity, and by passing a non-authority token to each of the respective subsequent controllers.

公开(公告)号：US11620231B2

公开(公告)日：2023-04-04

申请号：US17407248

申请日：2021-08-20

Applicant: International Business Machines Corporation

Inventor： Ram Sai Manoj Bamdhamravuri ,  Craig R. Walters ,  Christian Jacobi ,  Timothy Bronson ,  Gregory William Alexander ,  Hieu T. Huynh ,  Robert J. Sonnelitter, III ,  Jason D. Kohl ,  Deanna P. D. Berger ,  Richard Joseph Branciforte

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/123 ,  G06F12/0895

Abstract: Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

公开(公告)号：US12038841B2

公开(公告)日：2024-07-16

申请号：US17713264

申请日：2022-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tu-An T. Nguyen ,  Matthias Klein ,  Gregory William Alexander ,  Jason D. Kohl ,  Winston Herring ,  Timothy Bronson ,  Christian Jacobi

IPC: G06F12/08 ,  G06F9/34 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0897

CPC classification number: G06F12/084 ,  G06F9/34 ,  G06F9/3816 ,  G06F12/0815 ,  G06F12/0897

Abstract: Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

公开(公告)号：US11782777B1

公开(公告)日：2023-10-10

申请号：US17808119

申请日：2022-06-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gregory William Alexander ,  Deanna Postles Dunn Berger ,  Timothy Bronson ,  Lior Binyamini ,  Richard Joseph Branciforte ,  Guy G. Tracy

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/20 ,  G06F11/16

CPC classification number: G06F11/0724 ,  G06F11/0757 ,  G06F11/202 ,  G06F11/1608

Abstract: A method and a computer system for core recovery management are provided. A first operation signal is generated via a first hardware agent. The first operation signal indicates that the first hardware agent is processing an operation requested by a first processor core. The first processor core receives a first extend fence signal based on the generated first operation signal. As long as the first extend fence signal is received via the first processor core, the first processor core is kept in a fenced state for core recovery.

公开(公告)号：US11989128B1

公开(公告)日：2024-05-21

申请号：US18066575

申请日：2022-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Winston Herring ,  Gregory William Alexander ,  Timothy Bronson ,  Jason D Kohl

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0862

CPC classification number: G06F12/084 ,  G06F12/0833 ,  G06F12/0862

Abstract: A node of the computing environment obtains an exclusive fetch request of a cache line shared by, at least, the node and a manager node of the computing environment. The exclusive fetch request includes a state indication regarding processing of the exclusive fetch request by the manager node. The node processes the exclusive fetch request, based on the state indication included with the exclusive fetch request regarding processing of the exclusive fetch request by the manager node.

公开(公告)号：US20240104021A1

公开(公告)日：2024-03-28

申请号：US17934731

申请日：2022-09-23

Applicant: International Business Machines Corporation

Inventor： Michael Joseph Cadigan, JR. ,  Gregory William Alexander ,  Deanna Postles Dunn Berger ,  Timothy Bronson ,  Chung-Lung K. Shum ,  Aaron Tsai

IPC: G06F12/0891 ,  G06F12/0811

CPC classification number: G06F12/0891 ,  G06F12/0811

Abstract: Embodiments are for processor cross-core cache line contention management. A computer-implemented method includes sending a cross-invalidate command to one or more caches based on receiving a cache state change request for a cache line in a symmetric multiprocessing system and determining a retry delay based on receiving a cross-invalidate reject response from at least one of the one or more caches. The computer-implemented method also includes waiting until a retry delay period associated with the retry delay has elapsed to resend the cross-invalidate command to the one or more caches and granting the cache state change request for the cache line based on receiving a cross-invalidate accept response from the one or more caches.

公开(公告)号：US20230315637A1

公开(公告)日：2023-10-05

申请号：US17713263

申请日：2022-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gregory William Alexander ,  Tu-An T. Nguyen ,  Deanna Postles Dunn Berger ,  Timothy Bronson ,  CHRISTIAN JACOBI

IPC: G06F12/084 ,  G06F12/0831 ,  G06F9/30 ,  G06F7/58

CPC classification number: G06F12/084 ,  G06F12/0833 ,  G06F9/30134 ,  G06F7/584

Abstract: A computer-implemented method is provided. The method includes determining whether a rejection of a request is required and determining whether the request is software forward progress (SFP)-likely or SFP-unlikely upon determining that the rejection of the request is required. The method also includes executing a first pseudo random decision to set or not set a requested state of the request in an event the request is SFP-likely or SFP-unlikely, respectively, and rejecting the request following execution of the second pseudo random decision.

公开(公告)号：US20230315631A1

公开(公告)日：2023-10-05

申请号：US17709807

申请日：2022-03-31

Applicant: International Business Machines Corporation

Inventor： Yair Fried ,  Aaron Tsai ,  Eyal Naor ,  Christian Jacobi ,  Timothy Bronson ,  Chung-Lung K. Shum

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F2212/311

Abstract: Aspects include using a shadow copy of a level 1 (L1) cache in a cache hierarchy. A method includes maintaining the shadow copy of the L1 cache in the cache hierarchy. The maintaining includes updating the shadow copy of the L1 cache with memory content changes to the L1 cache a number of pipeline cycles after the L1 cache is updated with the memory content changes.

公开(公告)号：US12050538B2

公开(公告)日：2024-07-30

申请号：US17708785

申请日：2022-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robert J. Sonnelitter, III ,  Ekaterina M. Ambroladze ,  Timothy Bronson ,  Michael A. Blake ,  Tu-An T. Nguyen

IPC: G06F12/0891 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0817

CPC classification number: G06F12/0891 ,  G06F9/3816 ,  G06F12/0811 ,  G06F12/0824

Abstract: Castout handling in a distributed cache topology, including: detecting, by a first cache of a plurality of caches, a cache miss; providing, by the first cache to each other cache of the plurality of caches, a message comprising: data indicating a cache address corresponding to the cache miss; and data indicating a cache line to be evicted.

公开(公告)号：US11977486B2

公开(公告)日：2024-05-07

申请号：US17712510

申请日：2022-04-04

Applicant: International Business Machines Corporation

Inventor： Ashraf ElSharif ,  Richard Joseph Branciforte ,  Gregory William Alexander ,  Deanna Postles Dunn Berger ,  Timothy Bronson ,  Aaron Tsai ,  Taylor J. Pritchard ,  Markus Kaltenbach ,  Christian Jacobi ,  Michael A. Blake

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F2212/62

Abstract: A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.