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    Semiconductor device with apparatus for performing electrical tests on single memory cells
    1.
    发明授权
    Semiconductor device with apparatus for performing electrical tests on single memory cells 失效
    具有用于在单个存储器单元上执行电测试的装置的半导体器件

    公开(公告)号：US5235549A

    公开(公告)日：1993-08-10

    申请号：US814401

    申请日：1991-12-23

    申请人： Ian A. Young ,  Ananda G. Sarangi

    发明人： Ian A. Young ,  Ananda G. Sarangi

    IPC分类号： G11C29/02 ,  G11C29/50

    CPC分类号： G11C29/022 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5006

    摘要： A memory device having test circuitry incorporated into its design to enable direct external access to the bit lines of a single cell is described. When the device is put in test mode by applying external control signals, peripheral I/O circuitry is disabled. Once the I/O circuitry is disabled the test circuitry selects and enables the section of the array in which the selected cell is located through transfer circuits. The enabled transfer circuit for the selected section couples data between the selected cell and a set of predetermined I/O terminals.

    摘要翻译： 描述了具有并入其设计中的测试电路以使得能够直接外部访问单个单元的位线的存储器件。 当外部控制信号通过外部控制信号进入测试模式时，外设I / O电路被禁止。 一旦I / O电路被禁止，测试电路通过传输电路选择和启用所选单元所在阵列的部分。 所选部分的使能传输电路将所选择的单元和一组预定的I / O端子之间的数据进行耦合。

    NON-BOOLEAN ASSOCIATIVE PROCESSOR DEGREE OF MATCH AND WINNER TAKE ALL CIRCUITS
    3.
    发明申请
    NON-BOOLEAN ASSOCIATIVE PROCESSOR DEGREE OF MATCH AND WINNER TAKE ALL CIRCUITS 审中-公开

    公开(公告)号：US20170093377A1

    公开(公告)日：2017-03-30

    申请号：US14864241

    申请日：2015-09-24

    申请人： Dmitri E. Nikonov ,  Ian A. Young

    发明人： Dmitri E. Nikonov ,  Ian A. Young

    IPC分类号： H03K3/03 ,  G06K9/00

    CPC分类号： H03K3/0315 ,  G06K9/0055

    摘要： Embodiments include circuits, apparatuses, and systems for non-boolean associative processors. In embodiments, an electronic associative processor circuit may include first and second ring oscillators, each having an odd number of inverters, an input terminal, and an output terminal. A first capacitor may have a first terminal coupled with the output terminal of the first ring oscillator and a second capacitor may have a first terminal coupled with the output terminal of the second ring oscillator. Second terminals of the first and second capacitors may be coupled at an oscillator stage output terminal. The inverters of the first and second ring oscillators may be implemented with metal oxide semiconductor transistors. Other embodiments may be described and claimed.

    Magnetic state element and circuits
    4.
    发明授权
    Magnetic state element and circuits 有权
    磁状态元件和电路

    公开(公告)号：US09070468B2

    公开(公告)日：2015-06-30

    申请号：US13996998

    申请日：2012-03-29

    申请人： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

    发明人： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

    IPC分类号： G11C11/00 ,  G11C11/16 ,  H03K19/16

    CPC分类号： H01L29/66984 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697 ,  H01L27/226 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H03K19/16

    摘要： Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic demultiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.

    摘要翻译： 描述了一种用于自旋状态元件器件的装置，其包括：可变电阻磁极（VRM）器件，用于接收磁控制信号以调节VRM器件的电阻; 以及耦合到VRM装置的磁逻辑门控（MLG）装置，以接收磁逻辑输入并对磁逻辑输入执行逻辑运算，并且基于VRM装置的电阻来驱动输出磁信号。 描述了一种磁解多路复用器，其包括：第一VRM装置，用于接收磁控制信号以调整第一VRM的电阻; 第二VRM装置，用于接收所述磁控信号以调整所述第二VRM装置的电阻; 以及耦合到第一和第二VRM装置的MLG装置，MLG装置具有至少两个输出磁体，以基于第一和第二VRM装置的电阻输出磁信号。

    Automatic frequency control architecture with digital temperature compensation
    5.
    发明授权
    Automatic frequency control architecture with digital temperature compensation 有权
    具有数字温度补偿功能的自动频率控制架构

    公开(公告)号：US08274339B2

    公开(公告)日：2012-09-25

    申请号：US12770230

    申请日：2010-04-29

    申请人： Yongping Fan ,  Jing Li ,  Ian A. Young

    发明人： Yongping Fan ,  Jing Li ,  Ian A. Young

    IPC分类号： H03L1/02 ,  H03L7/085

    CPC分类号： H03L1/02 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1234 ,  H03B5/124 ,  H03B5/1265 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/103 ,  H03L7/18

    摘要： A mixed signal circuit architecture is disclosed for automatic frequency control and digital temperature compensation in an LC-PLL system. Some embodiments allow for high-volume manufacturing of products such as microprocessors and chipsets, and other circuits that employ LC-PLL technology. In some embodiments, various capacitor loadings can be selected to compensate for variation associated with process, voltage, temperature, and reference frequency. In addition, a multi-leg capacitor bank can be selectively used to further compensate for temperature variation post-lock, in accordance with some embodiments. A programmable timer can be used in some embodiments to allow for loop settling prior to assessing parameters of interest.

    摘要翻译： 公开了用于LC-PLL系统中的自动频率控制和数字温度补偿的混合信号电路架构。 一些实施例允许诸如微处理器和芯片组的产品的大量制造以及采用LC-PLL技术的其它电路。 在一些实施例中，可以选择各种电容器负载以补偿与过程，电压，温度和参考频率相关联的变化。 此外，根据一些实施例，可以选择性地使用多支脚电容器组来进一步补偿温度变化后锁定。 在一些实施例中可以使用可编程定时器，以便在评估感兴趣的参数之前允许循环结算。

    Clock distribution network having regulated power supply
    8.
    发明授权
    Clock distribution network having regulated power supply 有权

    公开(公告)号：US06650161B2

    公开(公告)日：2003-11-18

    申请号：US09751942

    申请日：2000-12-28

    申请人： Thomas P. Thomas ,  Ian A. Young

    发明人： Thomas P. Thomas ,  Ian A. Young

    IPC分类号： H03K300

    CPC分类号： G06F1/10

    摘要： A clock distribution network for an integrated circuit is disclosed. The network includes a plurality of inverters that distribute a clock signal. The inverters are powered by a power supply. The power supply is supplied to the inverters through a source follower transistor that has its gate connected to a regulated DC voltage. The source follower transistor operates in the saturation region.

    Clock distribution network utilizing local deskewing clock generator circuitry
    9.
    发明授权
    Clock distribution network utilizing local deskewing clock generator circuitry 失效
    时钟分配网络利用局部的歪斜时钟发生器电路

    公开(公告)号：US06229861B1

    公开(公告)日：2001-05-08

    申请号：US08486935

    申请日：1995-06-07

    申请人： Ian A. Young

    发明人： Ian A. Young

    IPC分类号： H04L700

    CPC分类号： G06F1/10

    摘要： A clock signal distribution network for a high-speed microprocessor includes a clock synthesizer coupled to receive an externally generated clock signal. The clock synthesizer deskews the external clock to generate an internal clock signal, which is then distributed about the semiconductor die by a conductivity tree. A set of local deskewing clock generators are coupled to branch interconnects of the tree and function as a zero-delay buffers for driving proximally located circuitry.

    摘要翻译： 用于高速微处理器的时钟信号分配网络包括被耦合以接收外部产生的时钟信号的时钟合成器。 时钟合成器对外部时钟进行校准以产生内部时钟信号，然后通过电导率树分布在半导体管芯周围。 一组本地的偏移时钟发生器耦合到树的分支互连，并且用作用于驱动向近侧定位的电路的零延迟缓冲器。

    Multiple synthesizer based timing signal generation scheme
    10.
    发明授权
    Multiple synthesizer based timing signal generation scheme 有权
    基于多合成器的定时信号生成方案

    公开(公告)号：US06172937B2

    公开(公告)日：2001-01-09

    申请号：US09309049

    申请日：1999-05-10

    申请人： Alper Ilkbahar ,  Simon M. Tam ,  Ian A. Young

    发明人： Alper Ilkbahar ,  Simon M. Tam ,  Ian A. Young

    IPC分类号： G11C800

    CPC分类号： G06F1/06

    摘要： A multiple synthesizer based timing signal generation scheme is described that allows accurate data and strobe generation in high speed source synchronous system interfaces. Multiple loop locked clock synthesizers (e.g., phase locked loops, delay locked loops) are used to generate multiple clock signals. Data and strobe signals are triggered off of transitions of one of the clock signals. Because multiple loop locked clock synthesizers are used to generate the clock signals, optimal or near optimal alignment of the data and strobe signals can be achieved. Improved alignment of the data and strobe signals provides improved data transmission rates.

    摘要翻译： 描述了基于多合成器的定时信号生成方案，其允许在高速源同步系统接口中进行准确的数据和频闪生成。 多环路锁定时钟合成器（例如，锁相环，延迟锁定环）用于产生多个时钟信号。 数据和选通信号从一个时钟信号的转换触发。 由于使用多个环路锁定时钟合成器来产生时钟信号，所以可以实现数据和选通信号的最佳或接近最佳对准。 改进的数据和选通信号的对准提供了改进的数据传输速率。