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1.发明授权Test assembly including a test die for testing a semiconductor product die 失效测试组件，包括用于测试半导体产品模具的测试模具公开(公告)号：US07557596B2
公开(公告)日：2009-07-07
申请号：US11000586
申请日：2004-11-30
IPC分类号： G01R31/02
CPC分类号： G01R1/07307 , G01R1/07342 , G01R1/07371 , G01R31/2884 , G01R31/2886 , H01L22/32 , H01L22/34 , H01L23/49811 , H01L24/05 , H01L2224/0401 , H01L2224/05553 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/06136 , H01L2224/13 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H05K3/20 , H05K3/3421 , H01L2924/00014 , H01L2924/00
摘要： One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die. The test die can be used to test multiple product die on one or more wafers.
摘要翻译： 本发明的一个实施例涉及一种用于测试产品模具的产品电路的测试组件。 在一个实施例中，测试组件包括在测试模具和用于将测试模具电耦合到与测试模具通信的主机控制器的互连衬底。 测试模具可以根据设计方法设计，包括在统一设计中同时设计测试电路和产品电路的步骤。 测试电路可以设计成为相应的产品电路提供高度的故障覆盖，通常不考虑测试电路所需的硅面积的量。 然后，设计方法将统一设计分为测试模具和产品模具。 测试芯片包括测试电路，产品芯片包括产品电路。 然后可以在单独的半导体晶片上制造产品和测试裸片。 通过将产品电路和测试电路划分为单独的管芯，可以在产品管芯上消除或最小化嵌入式测试电路。 这将倾向于减小产品模具的尺寸并降低制造产品模具的成本，同时保持产品模具内的产品电路的高度测试覆盖。 测试模具可用于在一个或多个晶片上测试多个产品模具。
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公开(公告)号：US06603324B2
公开(公告)日：2003-08-05
申请号：US09753312
申请日：2000-12-29
IPC分类号： G01R3102
CPC分类号： G01R1/07307 , G01R31/2884 , G01R31/31723 , H01L22/32 , H01L23/50 , H01L23/60 , H01L2224/0401 , H01L2224/05554 , H01L2224/16 , H01L2924/00013 , H01L2924/01079 , H01L2924/10253 , H01L2224/29099 , H01L2924/00
摘要： One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e.g., nonvolatile circuits) at the die or package level. The special contact points may also be used to select redundant circuits for faulty circuits.
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公开(公告)号：US06690185B1
公开(公告)日：2004-02-10
申请号：US09196924
申请日：1998-11-19
IPC分类号： G01R3102
CPC分类号： G01R1/07342 , G01R1/06716 , G01R3/00 , G01R31/2863 , G01R31/2889 , G01R31/2891
摘要： A method of fabricating a large contactor (62) is provided wherein one or more contactor units (78) are mounted on a support substrate (74) such that contact elements (80) attached to the contactor units are suitably aligned. In this manner, a large area contactor can be prepared using a plurality of smaller contactor units. Preferably the contact elements on the plurality of contactor units are coplanar across the contactor units. This is particularly advantageous for making a large contactor for probing semiconductor devices on a wafer. This also can be useful for making a contactor capable of contacting devices across an entire semiconductor wafer. In one embodiment, the contactor units self-align during reflow of a joining material such as solder balls (134) or other reflowable material interconnecting the contactor units and the support substrate. In alternative embodiments, alignment facilitation devices such as keys (154) and indentations (156) are utilized to assist the alignment of the contactor units.
摘要翻译： 提供一种制造大型接触器（62）的方法，其中一个或多个接触器单元（78）安装在支撑基板（74）上，使得附接到接触器单元的接触元件（80）被适当对准。 以这种方式，可以使用多个较小的接触器单元来制备大面积的接触器。 优选地，多个接触器单元上的接触元件在接触器单元之间是共面的。 这对于制造用于在晶片上探测半导体器件的大型接触器是特别有利的。 这也可以用于制造能够跨整个半导体晶片接触器件的接触器。 在一个实施例中，接触器单元在诸如焊球（134）或互连接触器单元和支撑衬底的其它可回流材料的接合材料的回流期间自对准。 在替代实施例中，利用诸如按键（154）和压痕（156）的对准促进装置来辅助接触器单元的对准。
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公开(公告)号：US06621260B2
公开(公告)日：2003-09-16
申请号：US09752795
申请日：2000-12-29
IPC分类号： G01R3128
CPC分类号： G01R1/07307 , G01R31/2884 , G01R31/31723 , H01L22/32 , H01L23/50 , H01L23/60 , H01L2224/0401 , H01L2224/05554 , H01L2224/16 , H01L2924/00013 , H01L2924/01079 , H01L2924/10253 , H01L2224/29099 , H01L2924/00
摘要： One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e.g., nonvolatile circuits) at the die or package level. The special contact points may also be used to select redundant circuits for faulty circuits.
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5.发明授权Test assembly including a test die for testing a semiconductor product die 失效测试组件，包括用于测试半导体产品模具的测试模具公开(公告)号：US06825052B2
公开(公告)日：2004-11-30
申请号：US10317486
申请日：2002-12-11
IPC分类号： G01R3126
CPC分类号： G01R1/07307 , G01R1/07342 , G01R1/07371 , G01R31/2884 , G01R31/2886 , H01L22/32 , H01L22/34 , H01L23/49811 , H01L24/05 , H01L2224/0401 , H01L2224/05553 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/06136 , H01L2224/13 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H05K3/20 , H05K3/3421 , H01L2924/00014 , H01L2924/00
摘要： One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die. The test die can be used to test multiple product die on one or more wafers.
摘要翻译： 本发明的一个实施例涉及一种用于测试产品模具的产品电路的测试组件。 在一个实施例中，测试组件包括在测试模具和用于将测试模具电耦合到与测试模具通信的主机控制器的互连衬底。 测试模具可以根据设计方法设计，包括在统一设计中同时设计测试电路和产品电路的步骤。 测试电路可以设计成为相应的产品电路提供高度的故障覆盖，通常不考虑测试电路所需的硅面积的量。 然后，设计方法将统一设计分为测试模具和产品模具。 测试芯片包括测试电路，产品芯片包括产品电路。 然后可以在单独的半导体晶片上制造产品和测试裸片。 通过将产品电路和测试电路划分为单独的管芯，可以在产品管芯上消除或最小化嵌入式测试电路。 这将倾向于减小产品模具的尺寸并降低制造产品模具的成本，同时保持产品模具内的产品电路的高度测试覆盖。 测试模具可用于在一个或多个晶片上测试多个产品模具。
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公开(公告)号：US06551844B1
公开(公告)日：2003-04-22
申请号：US09224673
申请日：1998-12-31
IPC分类号： H01L2166
CPC分类号： G01R1/07307 , G01R1/07342 , G01R1/07371 , G01R31/2884 , G01R31/2886 , H01L22/32 , H01L22/34 , H01L23/49811 , H01L24/05 , H01L2224/0401 , H01L2224/05553 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/06136 , H01L2224/13 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H05K3/20 , H05K3/3421 , H01L2924/00014 , H01L2924/00
摘要： One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die. The test die can be used to test multiple product die on one or more wafers.
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7.发明授权Special contact points for accessing internal circuitry of an integrated circuit 失效用于访问集成电路内部电路的特殊接点公开(公告)号：US06456099B1
公开(公告)日：2002-09-24
申请号：US09224169
申请日：1998-12-31
IPC分类号： G01R3102
CPC分类号： G01R1/07307 , G01R31/2884 , G01R31/31723 , H01L22/32 , H01L23/50 , H01L23/60 , H01L2224/0401 , H01L2224/05554 , H01L2224/16 , H01L2924/00013 , H01L2924/01079 , H01L2924/10253 , H01L2224/29099 , H01L2924/00
摘要： One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e.g., nonvolatile circuits) at the die or package level. The special contact points may also be used to select redundant circuits for faulty circuits.
摘要翻译： 本发明的一个实施例涉及包括接合焊盘和特殊接触焊盘或点的集成电路。 接合焊盘用于将集成电路作为整体与外部电路接口，并且将被连接到封装或电路板。 接合焊盘以预定的对准方式设置在管芯上，例如外围，栅格或中心对准。 特殊接触焊盘用于向内部电路提供外部测试模式和/或外部监测测试内部电路的结果。 特别的接触垫可以有利地以高度的位置自由度位于集成电路上。 对于一个实施例，特殊接触焊盘可以在与焊盘不同于对准的位置处设置在管芯上。 特殊的接触焊盘可以小于接合焊盘，以便不会由于特殊的接触垫而增加管芯的尺寸。 特殊接触点也可以用于在芯片或封装级别外部编程内部电路（例如非易失性电路）。 特殊接触点也可用于选择故障电路的冗余电路。
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8.发明授权Special contact points for accessing internal circuitry of an integrated circuit 失效用于访问集成电路内部电路的特殊接点公开(公告)号：US06940093B2
公开(公告)日：2005-09-06
申请号：US09753309
申请日：2000-12-29
CPC分类号： G01R1/07307 , G01R31/2884 , G01R31/31723 , H01L22/32 , H01L23/50 , H01L23/60 , H01L2224/0401 , H01L2224/05554 , H01L2224/16 , H01L2924/00013 , H01L2924/01079 , H01L2924/10253 , H01L2224/29099 , H01L2924/00
摘要： One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e.g., nonvolatile circuits) at the die or package level. The special contact points may also be used to select redundant circuits for faulty circuits.
摘要翻译： 本发明的一个实施例涉及包括接合焊盘和特殊接触焊盘或点的集成电路。 接合焊盘用于将集成电路作为整体与外部电路接口，并且将被连接到封装或电路板。 接合焊盘以预定的对准方式设置在管芯上，例如外围，栅格或中心对准。 特殊接触焊盘用于向内部电路提供外部测试模式和/或外部监测测试内部电路的结果。 特别的接触垫可以有利地以高度的位置自由度位于集成电路上。 对于一个实施例，特殊接触焊盘可以在与焊盘不同于对准的位置处设置在管芯上。 特殊的接触焊盘可以小于接合焊盘，以便不会由于特殊的接触垫而增加管芯的尺寸。 特殊接触点也可以用于在芯片或封装级别外部编程内部电路（例如非易失性电路）。 特殊接触点也可用于选择故障电路的冗余电路。
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9.发明授权Special contact points for accessing internal circuitry of an integrated circuit 失效用于访问集成电路内部电路的特殊接点公开(公告)号：US06597187B2
公开(公告)日：2003-07-22
申请号：US09752902
申请日：2000-12-29
IPC分类号： G01R3102
CPC分类号： G01R1/07307 , G01R31/2884 , G01R31/31723 , H01L22/32 , H01L23/50 , H01L23/60 , H01L2224/0401 , H01L2224/05554 , H01L2224/16 , H01L2924/00013 , H01L2924/01079 , H01L2924/10253 , H01L2224/29099 , H01L2924/00
摘要： An integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e.g., nonvolatile circuits) at the die or package level. The special contact points may also be used to select redundant circuits for faulty circuits.
摘要翻译： 一种集成电路，包括接合焊盘和特殊接触焊盘或点。 接合焊盘用于将集成电路作为整体与外部电路接口，并且将被连接到封装或电路板。 接合焊盘以预定的对准方式设置在管芯上，例如外围，栅格或中心对准。 特殊接触焊盘用于向内部电路提供外部测试模式和/或外部监测测试内部电路的结果。 特别的接触垫可以有利地以高度的位置自由度位于集成电路上。 对于一个实施例，特殊接触焊盘可以在与焊盘不同于对准的位置处设置在管芯上。 特殊的接触焊盘可以小于接合焊盘，以便不会由于特殊的接触垫而增加管芯的尺寸。 特殊接触点也可以用于在芯片或封装级别外部编程内部电路（例如非易失性电路）。 特殊接触点也可用于选择故障电路的冗余电路。
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公开(公告)号：US06429029B1
公开(公告)日：2002-08-06
申请号：US09224166
申请日：1998-12-31
IPC分类号： H01L2166
CPC分类号： G01R31/2884 , G01R31/2886 , H01L23/49811 , H01L24/06 , H01L24/13 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/06136 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H05K3/20 , H05K3/3421 , H01L2924/00014 , H01L2924/00
摘要： One embodiment of the present invention concerns a design methodology for generating a test die for a product die including the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die.
摘要翻译： 本发明的一个实施例涉及用于产生用于产品模具的测试模具的设计方法，包括在统一设计中同时设计测试电路和产品电路的步骤。 测试电路可以设计成为相应的产品电路提供高度的故障覆盖，通常不考虑测试电路所需的硅面积的量。 然后，设计方法将统一设计分为测试模具和产品模具。 测试芯片包括测试电路，产品芯片包括产品电路。 然后可以在单独的半导体晶片上制造产品和测试裸片。 通过将产品电路和测试电路划分为单独的管芯，可以在产品管芯上消除或最小化嵌入式测试电路。 这将倾向于减小产品模具的尺寸并降低制造产品模具的成本，同时保持产品模具内的产品电路的高度测试覆盖。
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