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    BIPOLAR CMOS SELECT DEVICE FOR RESISTIVE SENSE MEMORY
    2.
    发明申请
    BIPOLAR CMOS SELECT DEVICE FOR RESISTIVE SENSE MEMORY 有权
    BIPOLAR CMOS选择器件，用于电阻式感应存储器

    公开(公告)号：US20100177554A1

    公开(公告)日：2010-07-15

    申请号：US12502211

    申请日：2009-07-13

    申请人： Yong Lu ,  Hongyue Liu ,  Maroun Khoury ,  Yiran Chen

    发明人： Yong Lu ,  Hongyue Liu ,  Maroun Khoury ,  Yiran Chen

    IPC分类号： G11C11/00 ,  G11C11/14

    CPC分类号： G11C13/0004 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C2213/76

    摘要： A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.

    摘要翻译： 电阻式感测存储装置包括具有半导体衬底和设置在半导体衬底中并形成行或晶体管的多个晶体管的双极选择器件。 每个晶体管包括发射极触点和集电极触点。 每个集电极触点彼此电隔离，并且每个发射极触点彼此电隔离。 栅极触点沿发射极触点和集电极触点之间的沟道区域延伸。 基极触点设置在半导体衬底内，使得发射极触点和集电极触点位于栅极触点和基极触点之间。 电阻读出存储单元电耦合到每个集电极触点或发射极触点和位线。

    Active protection device for resistive random access memory (RRAM) formation
    5.
    发明授权
    Active protection device for resistive random access memory (RRAM) formation 有权
    用于电阻随机存取存储器（RRAM）形成的主动保护装置

    公开(公告)号：US07965538B2

    公开(公告)日：2011-06-21

    申请号：US12502224

    申请日：2009-07-13

    申请人： Yongchul Ahn ,  Antoine Khoueir ,  Shuiyuan Huang ,  Peter Nicholas Manos ,  Maroun Khoury

    发明人： Yongchul Ahn ,  Antoine Khoueir ,  Shuiyuan Huang ,  Peter Nicholas Manos ,  Maroun Khoury

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/78 ,  G11C2213/79

    摘要： Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal. A formation current is applied through the RRAM cell, and an activation voltage is concurrently applied to the APD to maintain a maximum magnitude of the formation current below a predetermined threshold level.

    摘要翻译： 在用于准备用于正常读写操作的单元的RRAM形成过程期间，向电阻随机存取存储器（RRAM）单元提供过电流保护的装置和方法。 根据各种实施例，RRAM单元连接在第一控制线和第二控制线之间，并且主动保护装置（APD）连接在第二控制线和电接地端之间。 通过RRAM单元施加形成电流，并且将激活电压同时施加到APD以将形成电流的最大幅度维持在预定阈值水平以下。

    Active Protection Device for Resistive Random Access Memory (RRAM) Formation
    8.
    发明申请
    Active Protection Device for Resistive Random Access Memory (RRAM) Formation 有权
    用于电阻随机存取存储器（RRAM）形成的主动保护装置

    公开(公告)号：US20110007552A1

    公开(公告)日：2011-01-13

    申请号：US12502224

    申请日：2009-07-13

    申请人： Yongchul Ahn ,  Antoine Khoueir ,  Shuiyuan Huang ,  Peter Nicholas Manos ,  Maroun Khoury

    发明人： Yongchul Ahn ,  Antoine Khoueir ,  Shuiyuan Huang ,  Peter Nicholas Manos ,  Maroun Khoury

    IPC分类号： G11C11/00 ,  G11C5/14

    CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/78 ,  G11C2213/79

    摘要： Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal. A formation current is applied through the RRAM cell, and an activation voltage is concurrently applied to the APD to maintain a maximum magnitude of the formation current below a predetermined threshold level

    摘要翻译： 在用于准备用于正常读写操作的单元的RRAM形成过程期间，向电阻随机存取存储器（RRAM）单元提供过电流保护的装置和方法。 根据各种实施例，RRAM单元连接在第一控制线和第二控制线之间，并且主动保护装置（APD）连接在第二控制线和电接地端之间。 通过RRAM单元施加形成电流，并且激活电压同时施加到APD以将形成电流的最大幅度维持在预定阈值水平以下

    Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors
    9.
    发明授权
    Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors 有权
    改善场效应晶体管负偏压温度不稳定性（NBTI）寿命的技术

    公开(公告)号：US07256087B1

    公开(公告)日：2007-08-14

    申请号：US11018422

    申请日：2004-12-21

    申请人： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

    发明人： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823842

    摘要： In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.

    摘要翻译： 在一个实施例中，集成电路包括具有包括P +掺杂栅极多晶硅层和氮化栅极氧化物（NGOX）层的栅极堆叠的PMOS晶体管。 NGOX层可以在硅衬底之上。 集成电路还包括形成在晶体管上的互连线。 互连线包括吸氢材料，并且可以包括单一材料或材料堆。 互连线有利地吸收否则将被捕获在NGOX层/硅衬底界面中的氢（例如，H 2 H 2或H 2 O 2），从而提高负偏压温度 晶体管的不稳定性（NBTI）寿命。