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    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENERGY EFFICIENT PROCESSOR THERMAL THROTTLING USING DEEP POWER DOWN MODE
    1.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENERGY EFFICIENT PROCESSOR THERMAL THROTTLING USING DEEP POWER DOWN MODE 有权
    能源效率和能源保护的方法，装置和系统，包括能源效率处理器使用深度掉电模式的热力

    公开(公告)号：US20120166839A1

    公开(公告)日：2012-06-28

    申请号：US13335831

    申请日：2011-12-22

    申请人： Inder M. Sodhi ,  Efraim Rotem ,  Alon Naveh ,  Sanjeev S. Jahagirdar ,  Varghese George

    发明人： Inder M. Sodhi ,  Efraim Rotem ,  Alon Naveh ,  Sanjeev S. Jahagirdar ,  Varghese George

    IPC分类号： G06F1/32

    CPC分类号： G06F1/206 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/16 ,  Y02D10/171

    摘要： Embodiments of the invention relate to energy efficient and conserving thermal throttling of electronic device processors using a zero voltage processor state. For example, a processor die may include a power control unit (PCU), and an execution unit having power gates and a thermal sensor. The PCU is attached to the thermal sensor to determine if a temperature of the execution unit has increased to greater than an upper threshold, such as while the execution unit is processing data in an active processor power state. The PCU is also attached to the power gates so that upon such detection, it can change the active processor power state to a zero processor power state to reduce the temperature of the execution unit. When the sensor detects that the temperature has decreased to less than a lower threshold, the PCU can change the processor power state back to the active state.

    摘要翻译： 本发明的实施例涉及使用零电压处理器状态的电子设备处理器的节能和节省热节流。 例如，处理器管芯可以包括功率控制单元（PCU）和具有电源门和热传感器的执行单元。 PCU连接到热传感器，以确定执行单元的温度是否已经增加到大于上限阈值，例如当执行单元处理处于活动处理器电源状态的数据时。 PCU也连接到电源门，因此在这种检测时，它可以将主处理器的电源状态改变到零处理器电源状态，以降低执行单元的温度。 当传感器检测到温度降低到低于下限阈值时，PCU可以将处理器电源状态改变回活动状态。

    Method, apparatus, and system for energy efficiency and energy conservation including energy efficient processor thermal throttling using deep power down mode
    2.
    发明授权
    Method, apparatus, and system for energy efficiency and energy conservation including energy efficient processor thermal throttling using deep power down mode 有权
    节能和节能的方法，装置和系统，包括使用深度掉电模式的节能处理器热节流

    公开(公告)号：US09122464B2

    公开(公告)日：2015-09-01

    申请号：US13335831

    申请日：2011-12-22

    申请人： Inder M. Sodhi ,  Efraim Rotem ,  Alon Naveh ,  Sanjeev S. Jahagirdar ,  Varghese George

    发明人： Inder M. Sodhi ,  Efraim Rotem ,  Alon Naveh ,  Sanjeev S. Jahagirdar ,  Varghese George

    IPC分类号： G06F1/00 ,  G06F1/20 ,  G06F1/32

    CPC分类号： G06F1/206 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/16 ,  Y02D10/171

    摘要： Embodiments of the invention relate to energy efficient and conserving thermal throttling of electronic device processors using a zero voltage processor state. For example, a processor die may include a power control unit (PCU), and an execution unit having power gates and a thermal sensor. The PCU is attached to the thermal sensor to determine if a temperature of the execution unit has increased to greater than an upper threshold, such as while the execution unit is processing data in an active processor power state. The PCU is also attached to the power gates so that upon such detection, it can change the active processor power state to a zero processor power state to reduce the temperature of the execution unit. When the sensor detects that the temperature has decreased to less than a lower threshold, the PCU can change the processor power state back to the active state.

    摘要翻译： 本发明的实施例涉及使用零电压处理器状态的电子设备处理器的节能和节省热节流。 例如，处理器管芯可以包括功率控制单元（PCU）和具有电源门和热传感器的执行单元。 PCU连接到热传感器，以确定执行单元的温度是否已经增加到大于上限阈值，例如当执行单元处理处于活动处理器电源状态的数据时。 PCU也连接到电源门，因此在这种检测时，它可以将主处理器的电源状态改变到零处理器电源状态，以降低执行单元的温度。 当传感器检测到温度降低到低于下限阈值时，PCU可以将处理器电源状态改变回活动状态。

    Extension of CPU context-state management for micro-architecture state
    6.
    发明授权
    Extension of CPU context-state management for micro-architecture state 有权
    扩展用于微架构状态的CPU上下文状态管理

    公开(公告)号：US09361101B2

    公开(公告)日：2016-06-07

    申请号：US13538252

    申请日：2012-06-29

    申请人： Efraim Rotem ,  Eliezer Weissmann ,  Michael Mishaeli ,  Boris Ginzburg ,  Alon Naveh

    发明人： Efraim Rotem ,  Eliezer Weissmann ,  Michael Mishaeli ,  Boris Ginzburg ,  Alon Naveh

    IPC分类号： G06F9/46 ,  G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/30043 ,  G06F9/30123 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/461

    摘要： A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a micro-architectural state and an architectural state of a processor in a common buffer of a memory upon a context switch that suspends the execution of a process. The micro-architectural state contains performance data resulting from the execution of the process. A restore instruction is executed to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process. Power management hardware then uses the micro-architectural state as an intermediate starting point for the resumed execution.

    摘要翻译： 处理器可以节省微架构上下文以提高代码执行和电源管理的效率。 执行保存指令以在停止进程的执行的上下文切换时将微架构状态和处理器的体系结构状态存储在存储器的公共缓冲器中。 微架构状态包含执行该过程所产生的性能数据。 执行恢复指令以在恢复执行该过程时从公共缓冲器检索微架构状态和架构状态。 电源管理硬件然后使用微架构状态作为恢复执行的中间起点。

    Controlling current transients in a processor
    7.
    发明授权
    Controlling current transients in a processor 有权
    控制处理器中的电流瞬变

    公开(公告)号：US09092210B2

    公开(公告)日：2015-07-28

    申请号：US13307529

    申请日：2011-11-30

    申请人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

    发明人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

    IPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/32

    CPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/3206

    摘要： In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括具有前端单元的核心，至少一个执行单元和后端单元。 当检测到的电压低于阈值电压时，多个电压降检测器可以位于每个核心内以输出电压降信号。 反过来，耦合以接收电压降信号的电流瞬态逻辑可以响应于接收到电压降信号而控制前端单元，执行单元和后端单元中的至少一个的微架构参数。 描述和要求保护其他实施例。

    Controlling Current Transients In A Processor
    8.
    发明申请
    Controlling Current Transients In A Processor 有权
    控制处理器中的电流瞬变

    公开(公告)号：US20120166854A1

    公开(公告)日：2012-06-28

    申请号：US13307529

    申请日：2011-11-30

    申请人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

    发明人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

    IPC分类号： G06F1/26

    CPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/3206

    摘要： In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括具有前端单元的核心，至少一个执行单元和后端单元。 当检测到的电压低于阈值电压时，多个电压降检测器可以位于每个核心内以输出电压降信号。 反过来，耦合以接收电压降信号的电流瞬态逻辑可以响应于接收到电压降信号而控制前端单元，执行单元和后端单元中的至少一个的微架构参数。 描述和要求保护其他实施例。

    Controlling standby power of low power devices
    10.
    发明授权
    Controlling standby power of low power devices 有权
    控制低功耗设备的待机功率

    公开(公告)号：US07401241B2

    公开(公告)日：2008-07-15

    申请号：US10875005

    申请日：2004-06-22

    申请人： Efraim Rotem ,  Alon Naveh ,  Avner Kornfeld ,  Tsvika Kurts

    发明人： Efraim Rotem ,  Alon Naveh ,  Avner Kornfeld ,  Tsvika Kurts

    IPC分类号： G06F1/32 ,  G06F1/00 ,  G05F3/02

    CPC分类号： G06F1/3203

    摘要： Systems and methods of managing power provide for applying a voltage from a voltage regulator to a component of a computing system and reducing the voltage based on a power saving parameter that is dedicated to the component. The reduction can be in conjunction with the entry of the component into a low power state such as a standby state or an off state, where the power saving parameter defines a voltage such as a minimum operating voltage or minimum sustainable voltage for the component, respectively. In one embodiment, the component is a central processing unit.

    摘要翻译： 管理电力的系统和方法提供了将电压从电压调节器施加到计算系统的部件，并且基于专用于部件的功率节省参数来降低电压。 减少可以与部件进入低功率状态（例如待机状态或关闭状态）一起进行，其中功率节省参数分别定义诸如组件的最小工作电压或最小可持续电压的电压 。 在一个实施例中，组件是中央处理单元。