公开(公告)号：US09652018B2

公开(公告)日：2017-05-16

申请号：US13997200

申请日：2011-12-30

申请人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Alon Naveh ,  Eliezer Weissmann

发明人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Alon Naveh ,  Eliezer Weissmann

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3206 ,  G06F1/26 ,  G06F1/3203

摘要： Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.

公开(公告)号：US09092210B2

公开(公告)日：2015-07-28

申请号：US13307529

申请日：2011-11-30

申请人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

发明人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

IPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/32

CPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/3206

摘要： In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括具有前端单元的核心，至少一个执行单元和后端单元。 当检测到的电压低于阈值电压时，多个电压降检测器可以位于每个核心内以输出电压降信号。 反过来，耦合以接收电压降信号的电流瞬态逻辑可以响应于接收到电压降信号而控制前端单元，执行单元和后端单元中的至少一个的微架构参数。 描述和要求保护其他实施例。

公开(公告)号：US20120166854A1

公开(公告)日：2012-06-28

申请号：US13307529

申请日：2011-11-30

申请人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

发明人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Eliezer Weissmann ,  Michael Zelikson

IPC分类号： G06F1/26

CPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/3206

摘要： In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括具有前端单元的核心，至少一个执行单元和后端单元。 当检测到的电压低于阈值电压时，多个电压降检测器可以位于每个核心内以输出电压降信号。 反过来，耦合以接收电压降信号的电流瞬态逻辑可以响应于接收到电压降信号而控制前端单元，执行单元和后端单元中的至少一个的微架构参数。 描述和要求保护其他实施例。

公开(公告)号：US20140245034A1

公开(公告)日：2014-08-28

申请号：US13997200

申请日：2011-12-30

申请人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Alon Naveh ,  Eliezer Weissmann

发明人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Alon Naveh ,  Eliezer Weissmann

IPC分类号： G06F1/26

CPC分类号： G06F1/3206 ,  G06F1/26 ,  G06F1/3203

摘要： Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.

摘要翻译： 描述与多级CPU（中央处理单元）高电流保护有关的方法和装置。 在一个实施例中，可以基于微架构事件（诸如uop（微操作）类型和大小）和/或数据类型，向不同的工作负载分配不同的许可证类型和/或权重。 还公开并要求保护其他实施例。

公开(公告)号：US20190004582A1

公开(公告)日：2019-01-03

申请号：US15635307

申请日：2017-06-28

申请人： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

发明人： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3296

摘要： In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

公开(公告)号：US20170371401A1

公开(公告)日：2017-12-28

申请号：US15190417

申请日：2016-06-23

申请人： Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nir Rosenzweig ,  Eric Distefano ,  Ishmael F. Santos ,  James G. Hermerding, II

发明人： Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nir Rosenzweig ,  Eric Distefano ,  Ishmael F. Santos ,  James G. Hermerding, II

IPC分类号： G06F1/32 ,  G06F9/30

CPC分类号： G06F1/3296 ,  G06F1/3228 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3851

摘要： In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

公开(公告)号：US20150355705A1

公开(公告)日：2015-12-10

申请号：US14298171

申请日：2014-06-06

申请人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

发明人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/0757 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

摘要： In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括多个核心和功率控制器。 功率控制器可以包括硬件占空比（HDC）逻辑，以便即使逻辑处理器具有要执行的工作负载来使得一个核的至少一个逻辑处理器进入强制空闲状态。 此外，如果至少另外一个其他逻辑处理器被阻止进入强制空闲状态，则HDC逻辑可以导致逻辑处理器在空闲周期结束之前退出强制空闲状态。 描述和要求保护其他实施例。

公开(公告)号：US20160026479A1

公开(公告)日：2016-01-28

申请号：US14338692

申请日：2014-07-23

申请人： Nir Rosenzweig ,  Efraim Rotem ,  Doron Rajwan ,  Nadav Shulman ,  Eliezer Weissmann

发明人： Nir Rosenzweig ,  Efraim Rotem ,  Doron Rajwan ,  Nadav Shulman ,  Eliezer Weissmann

IPC分类号： G06F9/445 ,  G06F13/42 ,  G06F12/08

CPC分类号： G06F9/44505 ,  G06F1/324 ,  G06F12/0844 ,  G06F13/4234 ,  G06F2212/1052 ,  G06F2212/604 ,  Y02D10/14 ,  Y02D10/151

摘要： In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (fCL). The processor also includes a power management unit (PMU) including fCL logic to determine whether to adjust the fCL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括耦合至少一个核心和高速缓冲存储器的至少一个核心和互连。 互连以互连频率（fCL）运行。 处理器还包括功率管理单元（PMU），其包括fCL逻辑以确定是否响应于与要由处理器处理的工作负载的可伸缩性相关联的贝叶斯预测值来调整fCL。 可以基于与处理器相关联的一个或多个活动度量来确定贝叶斯预测值。 描述和要求保护其他实施例。

公开(公告)号：US20180039322A1

公开(公告)日：2018-02-08

申请号：US15227040

申请日：2016-08-03

申请人： Eliezer Weissmann ,  Nir Rosenzweig ,  Efraim Rotem ,  Yoav Ben-Raphael ,  Alon Naveh

发明人： Eliezer Weissmann ,  Nir Rosenzweig ,  Efraim Rotem ,  Yoav Ben-Raphael ,  Alon Naveh

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

摘要： In one embodiment, a processor includes: a plurality of cores; a power controller including a logic to autonomously demote a first request for at least one core of the plurality of cores to enter a first low power state, to cause the at least one core to enter a second low power state, the first low power state a deeper low power state than the second low power state; and an interface to receive an input from a system software, the input including at least one demotion control parameter, where the logic is to autonomously demote the first request based at least in part on the at least one demotion control parameter. Other embodiments are described and claimed.

公开(公告)号：US20190196573A1

公开(公告)日：2019-06-27

申请号：US15849995

申请日：2017-12-21

申请人： Nikhil Gupta ,  Israel Hirsh ,  Esfir Natanzon ,  Nir Rosenzweig ,  Efraim Rotem ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

发明人： Nikhil Gupta ,  Israel Hirsh ,  Esfir Natanzon ,  Nir Rosenzweig ,  Efraim Rotem ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC分类号： G06F1/32 ,  G06F1/28

CPC分类号： G06F1/3293 ,  G06F1/28

摘要： In one embodiment, a processor includes: one or more cores to execute instructions; a first request register to store hardware performance state control information for a first core of the one or more cores obtained from an operating system; a second request register to store hardware performance state control override information, the hardware performance state control override information to be received from a management controller coupled to the processor; and a power controller coupled to the one or more cores to control a performance state of the first core based at least in part on the hardware performance state override information when at least one override indicator of the second request register is set. Other embodiments are described and claimed.