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    Method of manufacturing a semiconductor device utilzing two hard masks and two auxiliary masks to form PN junctions structure
    1.
    发明授权
    Method of manufacturing a semiconductor device utilzing two hard masks and two auxiliary masks to form PN junctions structure 有权

    公开(公告)号：US12087812B2

    公开(公告)日：2024-09-10

    申请号：US17374046

    申请日：2021-07-13

    Applicant: Infineon Technologies AG

    Inventor： Andreas Voerckel

    IPC: H01L21/761 ,  H01L21/04 ,  H01L21/76 ,  H01L29/06 ,  H01L29/16

    CPC classification number: H01L29/0634 ,  H01L21/0465 ,  H01L21/7602 ,  H01L21/761 ,  H01L29/1608

    Abstract: In an example, a first hard mask is formed on a first surface of a semiconductor body, wherein first openings in the first hard mask expose first surface sections and second openings in the first hard mask expose second surface sections. First dopants of a first conductivity type are implanted selectively through the first openings into the semiconductor body. Second dopants of a second conductivity type are implanted selectively through the second openings into the semiconductor body. The second conductivity type is complementary to the first conductivity type. A second hard mask is formed that covers the first surface sections and the second surface sections, wherein third openings in the second hard mask expose third surface sections and fourth openings in the second hard mask expose fourth surface sections. Third dopants of the first conductivity type are implanted selectively through the third openings into the semiconductor body. Fourth dopants of the second conductivity type are implanted selectively through the fourth openings into the semiconductor body.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230045841A1

    公开(公告)日：2023-02-16

    申请号：US17883716

    申请日：2022-08-09

    Applicant: Infineon Technologies AG

    Inventor： Andreas Voerckel

    IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L21/04

    Abstract: A semiconductor device includes a transistor. The transistor may include a gate electrode in gate trenches formed in a first portion of a silicon carbide substrate and extending in a first horizontal direction. The gate trenches pattern the first portion into ridges. The transistor may further include a source region, a channel region, and a drift region. The source region, channel region and part of the drift region may be arranged in the ridges. A current path from the source region to the drift region may extend in a depth direction of the silicon carbide substrate. The transistor may further include a body contact portion arranged in a second portion of the silicon carbide substrate. The second portion is adjacent to the first portion and extends in a second horizontal direction intersecting the first horizontal direction.

    Semiconductor device, junction field effect transistor and vertical field effect transistor
    6.
    发明授权
    Semiconductor device, junction field effect transistor and vertical field effect transistor 有权
    半导体器件，结场效应晶体管和垂直场效应晶体管

    公开(公告)号：US09029974B2

    公开(公告)日：2015-05-12

    申请号：US14023819

    申请日：2013-09-11

    Applicant: Infineon Technologies AG

    Inventor： Romain Esteve ,  Jens Konrath ,  Daniel Kueck ,  David Laforet ,  Cedric Ouvrard ,  Roland Rupp ,  Andreas Voerckel ,  Wolfgang Werner

    IPC: H01L29/47 ,  H01L29/78 ,  H01L29/06 ,  H01L29/812 ,  H01L29/872

    CPC classification number: H01L29/7827 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/872

    Abstract: A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate.

    Abstract translation: 根据实施例的半导体器件至少部分地布置在衬底中或衬底上，并且包括形成台面的凹部，其中台面沿着进入衬底的方向延伸到凹部的底平面，并且包括第一 导电类型，台面的半导体材料至少局部地包括不比底平面进一步延伸到衬底中的第一掺杂浓度。 所述半导体器件还包括至少部分地沿着台面的侧壁布置的导电结构，该导电结构与台面的半导体材料形成肖特基或肖特基状的电接触，其中所述衬底包括所述半导体材料的半导体材料， 所述第一导电类型至少局部地包括沿所述台面的投影到所述衬底中的与所述第一掺杂浓度不同的第二掺杂浓度。

    SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THEREOF
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THEREOF 有权

    公开(公告)号：US20230051830A1

    公开(公告)日：2023-02-16

    申请号：US17886533

    申请日：2022-08-12

    Applicant: Infineon Technologies AG

    Inventor： Andreas Voerckel ,  Hans Weber ,  Tobias Franz Wolfgang Hoechbauer

    IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L21/04

    Abstract: A transistor device and a method for forming a transistor device are disclosed. The transistor device includes: a SiC semiconductor body that includes a first semiconductor layer and a second semiconductor layer formed on top of the first semiconductor; a trench structure extending from a first surface of the semiconductor body through the second semiconductor layer into the first semiconductor layer; a drain region arranged in the first semiconductor layer; and a plurality of transistor cells each coupled between the drain region and a source node. The trench structure subdivides the second semiconductor layer into a plurality of mesa regions and includes at least one cavity. At least one of the plurality of transistor cells is at least partially integrated in each of the mesa regions.

    SEMICONDUCTOR DEVICE, JUNCTION FIELD EFFECT TRANSISTOR AND VERTICAL FIELD EFFECT TRANSISTOR
    10.
    发明申请
    SEMICONDUCTOR DEVICE, JUNCTION FIELD EFFECT TRANSISTOR AND VERTICAL FIELD EFFECT TRANSISTOR 有权
    半导体器件，连接场效应晶体管和垂直场效应晶体管

    公开(公告)号：US20150069411A1

    公开(公告)日：2015-03-12

    申请号：US14023819

    申请日：2013-09-11

    Applicant: Infineon Technologies AG

    Inventor： Romain Esteve ,  Jens Konrath ,  Daniel Kueck ,  David Laforet ,  Cedric Ouvrard ,  Roland Rupp ,  Andreas Voerckel ,  Wolfgang Werner

    IPC: H01L29/78 ,  H01L29/812 ,  H01L29/06

    CPC classification number: H01L29/7827 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/872

    Abstract: A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate.

    Abstract translation: 根据实施例的半导体器件至少部分地布置在衬底中或衬底上，并且包括形成台面的凹部，其中台面沿着进入衬底的方向延伸到凹部的底平面，并且包括第一 导电类型，台面的半导体材料至少局部地包括不比底平面进一步延伸到衬底中的第一掺杂浓度。 所述半导体器件还包括至少部分地沿着台面的侧壁布置的导电结构，该导电结构与台面的半导体材料形成肖特基或肖特基状的电接触，其中所述衬底包括所述半导体材料的半导体材料， 所述第一导电类型至少局部地包括沿所述台面的投影到所述衬底中的与所述第一掺杂浓度不同的第二掺杂浓度。

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