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    SUBSTRATE AND METHOD FOR FABRICATION THEREOF
    3.
    发明申请
    SUBSTRATE AND METHOD FOR FABRICATION THEREOF 审中-公开

    公开(公告)号：US20180315692A1

    公开(公告)日：2018-11-01

    申请号：US15962404

    申请日：2018-04-25

    Applicant: Infineon Technologies AG

    Inventor： Carlo Marbella ,  Marc Dittes

    IPC: H01L23/498 ,  H01L21/48

    CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49822

    Abstract: A substrate and method of fabrication is disclosed. In one example, the substrate includes a first dielectric layer, a first and a second conductive trace arranged over the first dielectric layer and a second dielectric layer arranged between the first and second conductive traces and partially covering the first and second conductive traces, wherein an exposed part of the first and second conductive traces is exposed from the second dielectric layer at an interface and wherein a shape of the interface between the first and second conductive traces includes one or more of an angle, an edge, a curvature, a bulge, a step and an indentation.

    Substrate and method for fabrication thereof
    6.
    发明授权
    Substrate and method for fabrication thereof 有权

    公开(公告)号：US10181439B2

    公开(公告)日：2019-01-15

    申请号：US15962404

    申请日：2018-04-25

    Applicant: Infineon Technologies AG

    Inventor： Carlo Marbella ,  Marc Dittes

    IPC: H05K1/02 ,  H05K3/02 ,  H01L23/498 ,  H01L21/48

    Abstract: A substrate and method of fabrication is disclosed. In one example, the substrate includes a first dielectric layer, a first and a second conductive trace arranged over the first dielectric layer and a second dielectric layer arranged between the first and second conductive traces and partially covering the first and second conductive traces, wherein an exposed part of the first and second conductive traces is exposed from the second dielectric layer at an interface and wherein a shape of the interface between the first and second conductive traces includes one or more of an angle, an edge, a curvature, a bulge, a step and an indentation.

    Substrates for semiconductor packages
    7.
    发明授权
    Substrates for semiconductor packages 有权

    公开(公告)号：US10937709B2

    公开(公告)日：2021-03-02

    申请号：US16245363

    申请日：2019-01-11

    Applicant: Infineon Technologies AG

    Inventor： Carlo Marbella ,  Kheng-Jin Chan

    IPC: H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

    Abstract: A substrate includes a dielectric layer, a first metal bar, a plurality of first traces, a plurality of first openings, a second metal bar, and at least one second opening. The dielectric layer has a first major surface and a second major surface opposite to the first major surface. The first metal bar is on the first major surface. The plurality of first traces are on the first major surface. Each first trace is connected at one end to the first metal bar. The plurality of first openings expose the dielectric layer on the first major surface and intersect a first trace. The second metal bar is on the second major surface. The at least one second opening exposes the dielectric layer on the second major surface and intersects the second metal bar. The first openings are laterally offset with respect to the at least one second opening.

    SUBSTRATES FOR SEMICONDUCTOR PACKAGES
    8.
    发明申请
    SUBSTRATES FOR SEMICONDUCTOR PACKAGES 审中-公开

    公开(公告)号：US20200227330A1

    公开(公告)日：2020-07-16

    申请号：US16245363

    申请日：2019-01-11

    Applicant: Infineon Technologies AG

    Inventor： Carlo Marbella ,  Kheng-Jin Chan

    IPC: H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

    Abstract: A substrate includes a dielectric layer, a first metal bar, a plurality of first traces, a plurality of first openings, a second metal bar, and at least one second opening. The dielectric layer has a first major surface and a second major surface opposite to the first major surface. The first metal bar is on the first major surface. The plurality of first traces are on the first major surface. Each first trace is connected at one end to the first metal bar. The plurality of first openings expose the dielectric layer on the first major surface and intersect a first trace. The second metal bar is on the second major surface. The at least one second opening exposes the dielectric layer on the second major surface and intersects the second metal bar. The first openings are laterally offset with respect to the at least one second opening.

    Semiconductor Package Configured for Connection to a Board
    9.
    发明申请
    Semiconductor Package Configured for Connection to a Board 审中-公开
    半导体封装配置为连接到板

    公开(公告)号：US20160329292A1

    公开(公告)日：2016-11-10

    申请号：US15150515

    申请日：2016-05-10

    Applicant: Infineon Technologies AG

    Inventor： Carlo Marbella

    IPC: H01L23/00

    Abstract: A semiconductor package includes a plurality of contact areas having a specific contact area and a plurality of solder balls applied to the contact areas. Two or more specific solder balls are applied to the specific contact area, and a minimum distance between the two specific solder balls is set such that the two or more specific solder balls merge into one another when connecting them to a substrate in a reflow process.

    Abstract translation: 半导体封装包括具有特定接触区域的多个接触区域和施加到接触区域的多个焊球。 将两个或更多个特定的焊球施加到特定的接触区域，并且设定两个特定焊球之间的最小距离，使得两个或更多个特定焊球在回流过程中将其连接到衬底时彼此合并。

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