公开(公告)号：US20240030334A1

公开(公告)日：2024-01-25

申请号：US18352572

申请日：2023-07-14

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  Michaela Braun ,  Jan Ropohl ,  Matthias Zigldrum

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758

Abstract: In an embodiment, a Group III nitride-based semiconductor device includes: a multilayer Group III nitride-based structure including a first major surface; and a source electrode, a gate electrode and a drain electrode arranged on the first major surface. The gate electrode is laterally arranged between the source electrode and the drain electrode and a metallization structure arranged on the first major surface. The metallization structure includes an electrically insulating layer arranged on the source electrode, the gate electrode and the drain electrode and a conductive redistribution structure electrically connected to the source electrode, the gate electrode and the drain electrode. One or more cavities are located in the electrically insulating layer of the metallization structure.

公开(公告)号：US11302783B2

公开(公告)日：2022-04-12

申请号：US16694070

申请日：2019-11-25

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Jan Ropohl

IPC: H01L29/45 ,  H01L29/20 ,  H01L21/283 ,  H01L29/40 ,  H01L29/778

Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.

公开(公告)号：US20180350981A1

公开(公告)日：2018-12-06

申请号：US16100676

申请日：2018-08-10

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L29/78 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L29/10 ,  H01L29/66 ,  H01L23/528

CPC classification number: H01L29/7816 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L29/1095 ,  H01L29/66681

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor in the front surface, and a metallization structure arranged on the front surface. The metallization structure includes at least one cavity arranged in at least one dielectric layer. Related methods of manufacture are also described.

公开(公告)号：US20180277501A1

公开(公告)日：2018-09-27

申请号：US15986433

申请日：2018-05-22

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L23/66 ,  H01L49/02 ,  H01L23/48 ,  H03F3/193 ,  H01L29/78 ,  H01L21/768 ,  H03F3/21 ,  H01L23/522

CPC classification number: H01L23/66 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L29/7816 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2223/6683 ,  H03F3/193 ,  H03F3/21 ,  H03F2200/222 ,  H03F2200/411

Abstract: In an embodiment, a method includes forming a first opening in a front surface of a semiconductor substrate including a LDMOS transistor structure, and covering the first opening with a first layer to form an enclosed cavity defined by material of the semiconductor substrate and the first layer. The material of the first layer lines sidewalls of the enclosed cavity.

公开(公告)号：US10050139B2

公开(公告)日：2018-08-14

申请号：US15191937

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor in the front surface, and a metallization structure arranged on the front surface. The metallization structure includes at least one cavity arranged in at least one dielectric layer.

公开(公告)号：US20200168709A1

公开(公告)日：2020-05-28

申请号：US16694070

申请日：2019-11-25

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Jan Ropohl

IPC: H01L29/20 ,  H01L29/45 ,  H01L21/283 ,  H01L29/40

Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.

公开(公告)号：US10304789B2

公开(公告)日：2019-05-28

申请号：US15986433

申请日：2018-05-22

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/66 ,  H01L49/02 ,  H01L29/78 ,  H03F3/193 ,  H03F3/21 ,  H01L23/522

Abstract: In an embodiment, a method includes forming a first opening in a front surface of a semiconductor substrate including a LDMOS transistor structure, and covering the first opening with a first layer to form an enclosed cavity defined by material of the semiconductor substrate and the first layer. The material of the first layer lines sidewalls of the enclosed cavity.

公开(公告)号：US10020270B2

公开(公告)日：2018-07-10

申请号：US15279649

申请日：2016-09-29

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L23/66 ,  H01L29/78 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768 ,  H03F3/193 ,  H03F3/21

CPC classification number: H01L23/66 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2223/6683 ,  H03F3/193 ,  H03F3/21 ,  H03F2200/222 ,  H03F2200/411

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate including a front surface, an LDMOS transistor structure in the front surface, a conductive interconnection structure arranged on the front surface, and at least one cavity arranged in the front surface.

公开(公告)号：US11728389B2

公开(公告)日：2023-08-15

申请号：US17695366

申请日：2022-03-15

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Jan Ropohl

IPC: H01L29/45 ,  H01L29/20 ,  H01L21/283 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L21/283 ,  H01L29/401 ,  H01L29/452 ,  H01L29/778

Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.

公开(公告)号：US20220208972A1

公开(公告)日：2022-06-30

申请号：US17695366

申请日：2022-03-15

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Jan Ropohl

IPC: H01L29/20 ,  H01L21/283 ,  H01L29/40 ,  H01L29/45

Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.