公开(公告)号：US20230230951A1

公开(公告)日：2023-07-20

申请号：US18189500

申请日：2023-03-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshihito OTSUBO ,  Morio TAKEUCHI ,  Tsuyoshi TAKAKURA

IPC: H01L23/00 ,  H01L21/60 ,  H01L23/552 ,  H01L23/66 ,  H01L23/538

CPC classification number: H01L24/48 ,  H01L21/60 ,  H01L23/552 ,  H01L23/66 ,  H01L23/5386 ,  H01L2224/48227 ,  H01L2224/4912 ,  H01L24/49 ,  H01L2924/19101 ,  H01L2924/3025

Abstract: To provide a circuit module capable of suppressing a decrease in an area for mounting an electronic component on a substrate even when a wire for shielding the electronic component is connected to the substrate. A circuit module according to the present disclosure includes a substrate, a first component mounted on the substrate and including a ground terminal on an upper surface, first wires that connect the ground terminal to the substrate, and a second component mounted on the substrate, in which overlapping first wires in plan view.

公开(公告)号：US08749073B2

公开(公告)日：2014-06-10

申请号：US13154565

申请日：2011-06-07

Applicant: Junichi Nakamura ,  Kentaro Kaneko ,  Shunichiro Matsumoto

Inventor： Junichi Nakamura ,  Kentaro Kaneko ,  Shunichiro Matsumoto

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/642 ,  H01L24/16 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2924/1205 ,  H01L2924/1207 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19101 ,  H01L2924/19105 ,  H05K1/111 ,  H05K3/244 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2201/09072 ,  H05K2201/10015 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/308

Abstract: A wiring board includes a structure in which a plurality of wiring layers are stacked with insulating layers interposed therebetween, a plurality of pads for mounting an electronic component, the pads being formed on an outermost insulating layer on one surface side of the structure and exposed to the surface of the outermost insulating layer, and a recessed portion formed at a place corresponding to a mounting area for the electronic component. The recessed portion is formed in the outermost insulating layer at an area between the pads to which electrode terminals of the electronic component to be mounted are to be connected, respectively.

Abstract translation: 布线基板包括多个布线层层叠有绝缘层的结构，多个用于安装电子部件的焊盘，该焊盘形成在该结构的一个表面侧上的最外侧的绝缘层上并暴露于 最外层绝缘层的表面和形成在与电子部件的安装区域对应的位置的凹部。 凹陷部分分别形成在要连接的电子部件的电极端子的焊盘之间的区域中的最外层绝缘层中。

公开(公告)号：US20240312936A1

公开(公告)日：2024-09-19

申请号：US18604787

申请日：2024-03-14

Applicant: Infineon Technologies Austria AG

Inventor： Joon Shyan Tan ,  Lee Shuang Wang ,  Azlina Kassim ,  Teck Sim Lee ,  Kok Yau Chua ,  Chee Hong Lee ,  Zhihui Yuan

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L23/3107 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/08225 ,  H01L2224/45014 ,  H01L2224/48175 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19101

Abstract: A power semiconductor package includes: a first power semiconductor die arranged on and electrically coupled to a first side of a first die pad; a first passive electronic component having a first end and an opposite second end, the first end being arranged on and coupled to the first side of the first die pad and the second end being coupled to an internal ledge of a first external contact; a second passive electronic component connected in series with the first passive electronic component; and an encapsulation encapsulating the first power semiconductor die and the first and second passive electronic components. The first external contact is exposed from a first lateral side of the encapsulation.

公开(公告)号：US10083942B2

公开(公告)日：2018-09-25

申请号：US15524032

申请日：2015-11-03

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE

Inventor： Bastien Letowski ,  Jean-Christophe Crebier ,  Nicolas Rouger ,  Julie Widiez

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/07 ,  H01L23/367 ,  H01L25/18 ,  H01L23/498 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L25/071 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/3735 ,  H01L23/49805 ,  H01L24/26 ,  H01L24/32 ,  H01L25/072 ,  H01L25/074 ,  H01L25/18 ,  H01L2224/29013 ,  H01L2224/291 ,  H01L2224/3003 ,  H01L2224/3012 ,  H01L2224/32141 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19101 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: An electronic power device including: a first electronic power component in which all the electrodes are arranged at a first main face of the first electronic power component; and an electric contact element in which a first main face is arranged against the first main face of the first electronic power component and which includes plural separate electrically conductive portions to which the electrodes of the first electronic power component are electrically connected. The first electronic power component and the electric contact element together form a stack such that a first lateral face of each of the portions of the electric contact element, substantially perpendicular to the first main face of the electric contact element, is arranged against at least one metallization of a support forming an electric contact of the first electronic power component.

公开(公告)号：US20170338208A1

公开(公告)日：2017-11-23

申请号：US15524032

申请日：2015-11-03

Applicant: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE

Inventor： Bastien LETOWSKI ,  Jean-Christophe CREBIER ,  Nicolas ROUGER ,  Julie WIDIEZ

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/367 ,  H01L25/18 ,  H01L23/498 ,  H01L23/373

CPC classification number: H01L25/071 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/3735 ,  H01L23/49805 ,  H01L24/26 ,  H01L24/32 ,  H01L25/072 ,  H01L25/074 ,  H01L25/18 ,  H01L2224/29013 ,  H01L2224/291 ,  H01L2224/3003 ,  H01L2224/3012 ,  H01L2224/32141 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19101 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: An electronic power device including: a first electronic power component in which all the electrodes are arranged at a first main face of the first electronic power component; and an electric contact element in which a first main face is arranged against the first main face of the first electronic power component and which includes plural separate electrically conductive portions to which the electrodes of the first electronic power component are electrically connected. The first electronic power component and the electric contact element together form a stack such that a first lateral face of each of the portions of the electric contact element, substantially perpendicular to the first main face of the electric contact element, is arranged against at least one metallization of a support forming an electric contact of the first electronic power component.

公开(公告)号：US20150270208A1

公开(公告)日：2015-09-24

申请号：US14661054

申请日：2015-03-18

Applicant: Infineon Technologies Austria AG

Inventor： Ralf OTREMBA ,  Fabio BRUCCHI ,  Teck Sim LEE ,  Xaver SCHLOEGEL ,  Franz STUECKLER

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L23/49575 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49562 ,  H01L23/49589 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19101 ,  H01L2924/19105 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A power semiconductor device is provided. The power semiconductor device includes a leadframe, which includes a first chip carrier part and at least one second chip carrier part, which are fitted at a distance from one another and are in each case electrically conductive, at least one first power semiconductor component applied on the first chip carrier part, at least one second power semiconductor component applied on the second chip carrier part, external contacts in the form of external leads, and a capacitor. The capacitor is mounted on two adjacent external leads.

Abstract translation: 提供功率半导体器件。 所述功率半导体器件包括引线框架，所述引线框架包括第一芯片载体部分和至少一个第二芯片载体部分，所述第一芯片载体部分和至少一个第二芯片载体部分彼此间隔一定距离并且在每种情况下导电，至少一个第一功率半导体部件 第一芯片载体部分，施加在第二芯片载体部分上的至少一个第二功率半导体部件，外部引线形式的外部触点和电容器。 电容器安装在两个相邻的外部引线上。

公开(公告)号：US12057359B2

公开(公告)日：2024-08-06

申请号：US17884499

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Cheng Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  B29C45/14 ,  B29K63/00 ,  B29L31/34

CPC classification number: H01L23/3114 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/566 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0655 ,  B29C45/14655 ,  B29K2063/00 ,  B29K2995/0007 ,  B29L2031/3406 ,  H01L24/13 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81192 ,  H01L2924/1431 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19101 ,  H01L2924/3511 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/13113 ,  H01L2924/00014 ,  H01L2224/13118 ,  H01L2924/00014 ,  H01L2224/13149 ,  H01L2924/00014 ,  H01L2224/1312 ,  H01L2924/00014 ,  H01L2224/13109 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/1431 ,  H01L2924/00012

Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

公开(公告)号：US09813046B2

公开(公告)日：2017-11-07

申请号：US15087250

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Sameer Shekhar ,  Amit K. Jain ,  Pooja Nukala

IPC: H03K3/011 ,  H01L23/00 ,  H01L23/498 ,  H05K1/18 ,  H01L25/065

CPC classification number: H01L25/0655 ,  H01L23/49838 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1432 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19043 ,  H01L2924/19101 ,  H03K19/0005 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/10234 ,  H05K2201/10318 ,  H05K2201/10378

Abstract: Some embodiments include apparatus and methods using a package substrate and a die coupled to the package substrate. The package substrate includes conductive contacts, conductive paths coupled to the conductive contacts, and a resistor embedded in the package substrate. The die includes buffer circuits and a calibration module coupled to the buffer circuits and the resistor. The buffer circuits include output nodes coupled to the conductive contacts through the conductive paths. The calibration module is configured to perform a calibration operation to adjust resistances of the buffer circuits based on a value of a voltage at a terminal of the resistor during the calibration operation.

公开(公告)号：US20160322333A1

公开(公告)日：2016-11-03

申请号：US15137062

申请日：2016-04-25

Applicant: Infineon Technologies AG

Inventor： Edward FUERGUT ,  Martin GRUBER ,  Wolfram HABLE

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/473 ,  H01L25/00 ,  H01L23/00 ,  H01L25/07 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L23/473 ,  H01L24/32 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/074 ,  H01L25/50 ,  H01L2023/4031 ,  H01L2023/405 ,  H01L2023/4087 ,  H01L2224/023 ,  H01L2224/27464 ,  H01L2224/29082 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29184 ,  H01L2224/32225 ,  H01L2224/40225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/84205 ,  H01L2224/84801 ,  H01L2224/85205 ,  H01L2224/85801 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/1426 ,  H01L2924/1431 ,  H01L2924/186 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19101 ,  H01L2924/401 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Various embodiments provide an electronic module comprising a interposer comprising a fluid channel formed in an electrically isolating material and an electrically conductive structured layer; at least one electronic chip attached to the electrically conductive layer and in thermal contact to the fluid channel; and a molded encapsulation formed at least partially around the at least one electronic chip, wherein the electrically conductive structured layer is directly formed on the electrically isolating material.

Abstract translation: 各种实施例提供了一种电子模块，其包括插入器，其包括形成在电隔离材料中的流体通道和导电结构化层; 至少一个电子芯片附接到所述导电层并与所述流体通道热接触; 以及至少部分地围绕所述至少一个电子芯片形成的模制封装，其中所述导电结构化层直接形成在所述电绝缘材料上。

公开(公告)号：US09468098B2

公开(公告)日：2016-10-11

申请号：US14220913

申请日：2014-03-20

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Jonghae Kim ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Robert Paul Mikulka

IPC: H01L23/538 ,  H05K1/11 ,  H05K1/03 ,  H05K1/18 ,  H05K3/30 ,  H05K3/40 ,  H01L23/48 ,  H01L23/64 ,  H05K1/02 ,  H05K3/36 ,  H05K1/14 ,  H05K1/16 ,  H05K3/34

CPC classification number: H05K3/303 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/19101 ,  H05K1/0243 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/141 ,  H05K1/144 ,  H05K1/165 ,  H05K1/18 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4007 ,  H05K3/4015 ,  H05K2201/1003 ,  H05K2201/10477 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/041 ,  H05K2203/1316 ,  Y10T29/4902 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: Systems and methods relate to a semiconductor package comprising a first substrate or a 2D passive-on-glass (POG) structure with a passive component and a first set of one or more package pads formed on a face of a glass substrate. The semiconductor package also includes a second or laminate substrate with a second set of one or more package pads formed on a face of the second or laminate substrate. Solder balls are dropped, configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the first substrate or the 2D POG structure is placed face-up on the face of the second or laminate substrate. A printed circuit board (PCB) can be coupled to a bottom side of the second or laminate substrate.

Abstract translation: 系统和方法涉及包括第一衬底或2D无源玻璃（POG）结构的半导体封装，其具有无源部件和形成在玻璃衬底的表面上的一个或多个封装焊盘的第一组。 半导体封装还包括具有第二组一个或多个封装焊盘的第二或层压衬底，其形成在第二层压衬底的表面上。 焊球被落下，被配置为使第一组一个或多个封装焊盘与第二组一个或多个封装焊盘接触，其中第一基板或2D POG结构朝上放置在第二或层压板的表面上 基质。 印刷电路板（PCB）可以耦合到第二或层压基板的底侧。