公开(公告)号：US09703562B2

公开(公告)日：2017-07-11

申请号：US13844881

申请日：2013-03-16

申请人： Intel Corporation

发明人： William C. Rash ,  Bret L. Toll ,  Scott D. Hahn ,  Glenn J. Hinton

IPC分类号： G06F9/30 ,  G06F9/40

CPC分类号： G06F9/30145 ,  G06F9/3017 ,  G06F9/30189

摘要： A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems.

公开(公告)号：US11373987B2

公开(公告)日：2022-06-28

申请号：US16646460

申请日：2017-12-28

申请人： Intel Corporation

发明人： Wilfred Gomes ,  Mark Bohr ,  Glenn J. Hinton ,  Rajesh Kumar

IPC分类号： H01L21/00 ,  H01L25/18 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

摘要： Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.

公开(公告)号：US10719443B2

公开(公告)日：2020-07-21

申请号：US16363992

申请日：2019-03-25

申请人： Intel Corporation

发明人： Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

IPC分类号： G11C11/406 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G11C14/00

摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US10564986B2

公开(公告)日：2020-02-18

申请号：US15388828

申请日：2016-12-22

申请人： Intel Corporation

发明人： Michael A. Rothman ,  Vincent J. Zimmer ,  Glenn J. Hinton ,  Barnes Cooper ,  Leena K. Puthiyedath

IPC分类号： G06F1/32 ,  G06F9/44 ,  G06F9/4401 ,  G06F1/3234

摘要： A disclosed example method to suspend and resume a device includes: after detecting a low-power suspend mode request, determining a storage performance of the device to store suspend state data; based on the storage performance of the device, setting a suspend flag to indicate a low-power suspend mode to a processor platform; when resuming from the low-power suspend mode, confirming a setting of a resume flag from the processor platform, the resume flag to notify an operating system to resume from the low-power suspend mode; and when the resume flag is set, restoring state data corresponding to an operating system context from a non-volatile dual-purpose system and storage memory.

公开(公告)号：US10365832B2

公开(公告)日：2019-07-30

申请号：US15633571

申请日：2017-06-26

申请人： Intel Corporation

发明人： Eric J. Dahlen ,  Glenn J. Hinton ,  Raj K. Ramanujan

IPC分类号： G06F3/06 ,  G06F12/0893 ,  G06F11/07 ,  G06F12/02 ,  G11C14/00 ,  G06F12/06 ,  G06F12/0868

摘要： Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

公开(公告)号：US20180181411A1

公开(公告)日：2018-06-28

申请号：US15388828

申请日：2016-12-22

申请人： Intel Corporation

发明人： Michael A. Rothman ,  Vincent J. Zimmer ,  Glenn J. Hinton ,  Barnes Cooper ,  Leena K. Puthiyedath

IPC分类号： G06F9/44 ,  G06F1/32

摘要： A disclosed example method to suspend and resume a device includes: after detecting a low-power suspend mode request, determining a storage performance of the device to store suspend state data; based on the storage performance of the device, setting a suspend flag to indicate a low-power suspend mode to a processor platform; when resuming from the low-power suspend mode, confirming a setting of a resume flag from the processor platform, the resume flag to notify an operating system to resume from the low-power suspend mode; and when the resume flag is set, restoring state data corresponding to an operating system context from a non-volatile dual-purpose system and storage memory.

公开(公告)号：US20160041772A1

公开(公告)日：2016-02-11

申请号：US14746734

申请日：2015-06-22

申请人： Intel Corporation

发明人： Eric J. Dahlen ,  Glenn J. Hinton ,  Raj K. Ramanujan

IPC分类号： G06F3/06

CPC分类号： G06F3/0611 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/0766 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0868 ,  G06F12/0893 ,  G06F2212/1024 ,  G06F2212/313 ,  G06F2212/7203 ,  G06F2212/7208 ,  G06F2212/7209 ,  G06F2212/7211 ,  G11C14/009

摘要： Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

摘要翻译： 本发明的实施例描述了包括两级存储器的系统主存储器，其包括系统盘级存储器的缓存子集。 该主存储器包括包括由易失性存储器构成的存储器的“近存储器”，以及包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。 远端存储器被呈现为主机OS的“主存储器”，而近端存储器是对于对OS是透明的远存储器的高速缓存，因此与OS显示与现有技术主存储器解决方案相同的高速缓存。 两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。 靠近存储器可以通过高带宽，低延迟的方式耦合到主机系统CPU，用于有效处理。 远存储器可以经由低带宽，高延迟装置耦合到CPU。

公开(公告)号：US09087584B2

公开(公告)日：2015-07-21

申请号：US14105708

申请日：2013-12-13

申请人： Intel Corporation

发明人： Eric J. Dahlen ,  Glenn J. Hinton ,  Raj K. Ramanujan

IPC分类号： G06F12/08 ,  G11C14/00 ,  G06F11/07 ,  G06F12/02

CPC分类号： G06F3/0611 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/0766 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/0868 ,  G06F12/0893 ,  G06F2212/1024 ,  G06F2212/313 ,  G06F2212/7203 ,  G06F2212/7208 ,  G06F2212/7209 ,  G06F2212/7211 ,  G11C14/009

摘要： Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

摘要翻译： 本发明的实施例描述了包括两级存储器的系统主存储器，其包括系统盘级存储器的缓存子集。 该主存储器包括包括由易失性存储器构成的存储器的“近存储器”，以及包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。 远端存储器被呈现为主机OS的“主存储器”，而近端存储器是对于对OS是透明的远存储器的高速缓存，因此与OS显示与现有技术主存储器解决方案相同的高速缓存。 两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。 靠近存储器可以通过高带宽，低延迟的方式耦合到主机系统CPU，用于有效处理。 远存储器可以经由低带宽，高延迟装置耦合到CPU。

公开(公告)号：USRE45487E1

公开(公告)日：2015-04-21

申请号：US13804519

申请日：2013-03-14

申请人： Intel Corporation

发明人： David J. Sager ,  Thomas D. Fletcher ,  Glenn J. Hinton ,  Michael D. Upton

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F15/76 ,  G06F9/44 ,  G06F1/04 ,  G06F15/00 ,  G06F9/00 ,  G06F1/02

CPC分类号： G06F1/02 ,  G06F1/06 ,  G06F1/08 ,  G06F9/30145 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3869 ,  G06F15/7832

摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

公开(公告)号：US11749663B2

公开(公告)日：2023-09-05

申请号：US17742205

申请日：2022-05-11

申请人： Intel Corporation

发明人： Wilfred Gomes ,  Mark Bohr ,  Glenn J. Hinton ,  Rajesh Kumar

IPC分类号： H01L21/00 ,  H01L25/18 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L25/18 ,  H01L23/481 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L2924/1431 ,  H01L2924/1436

摘要： Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.