公开(公告)号：US20240203853A1

公开(公告)日：2024-06-20

申请号：US18085281

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Hongxia Feng ,  Julianne Troiano ,  Dingying Xu ,  Matthew Tingey ,  Xiaoying Guo ,  Srinivas Venkata Ramanuja Pietambaram ,  Bai Nie ,  Gang Duan ,  Bin Mu ,  Kyle Mcelhinny ,  Ashay A. Dani ,  Leonel R. Arana

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L21/4846 ,  H01L23/5384

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a substrate, a via, a build-up layer, a top layer, and one or more dies. The substrate can include a conductor coating. The via can be connected to the conductor coating. The build-up layer can be on the substrate. The build-up layer can define a channel that the via is formed within and insulate the via during operation of the electronic device. The top layer can be interproximal to the substrate and the via. The one or more dies can be connected to the via.

公开(公告)号：US20240006298A1

公开(公告)日：2024-01-04

申请号：US17855040

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Steve Cho ,  Marcel Arlan Wall ,  Onur Ozkan ,  Ali Lehaf ,  Yi Yang ,  Jason Scott Steill ,  Gang Duan ,  Brandon C. Marin ,  Jeremy D. Ecton ,  Srinivas Venkata Ramanuja Pietambaram ,  Haifa Hariri ,  Bai Nie ,  Hiroki Tanaka ,  Kyle Mcelhinny ,  Jason Gamba ,  Venkata Rajesh Saranam ,  Kristof Darmawikarta ,  Haobo Chen

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L23/49816 ,  H01L21/4853 ,  H01L21/481 ,  H01L23/49838

Abstract: An electronic device may include an integrated circuit, for instance a semiconductor die. The electronic device may include a substrate having a first layer and a second layer. The first and second layers may include interconnects recessed below a surface of the substrate. The substrate may include a passivation layer directly coupled with portions of the interconnects. A solder resist material may at least partially cover portions of the passivation layer directly coupled with the first interconnect surface.