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公开(公告)号:US09817028B2
公开(公告)日:2017-11-14
申请号:US14866221
申请日:2015-09-25
Applicant: Intel Corporation
Inventor: Mayue Xie , Hemachandar Tanukonda Devarajulu , Deepak Goyal
IPC: G01R1/07 , G01R31/303 , G01R31/311
CPC classification number: G01R1/071 , G01R1/06772 , G01R31/303 , G01R31/311
Abstract: An apparatus comprises a contactless sense probe, an electro optic sensor module, and a test signal emitter circuit. The contactless sense probe includes a photoconductive switch and the signal bandwidth of the photoconductive switch is variable. The test signal emitter circuit configured to apply a test signal to a device under test (DUT) at a first location of the DUT, wherein the test signal includes a test signal frequency. The electro-optic sensor module is coupled to the contactless sense probe and configured to: generate an impulse signal at the contactless sense probe using an optical signal input to the first photoconductive switch; sense the test signal frequency in the impulse signal using the contactless sense probe at a second location of the DUT; and generate an indication of a defect in the DUT when the test signal frequency is undetected in the impulse signal.
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公开(公告)号:US20160043011A1
公开(公告)日:2016-02-11
申请号:US14876728
申请日:2015-10-06
Applicant: Intel Corporation
Inventor: Mayue Xie , Zhiyong Wang , Yuan-Chuan Steven Chen
CPC classification number: H01L22/34 , G01R31/2642 , H01L22/32 , H01L23/48 , H01L23/50 , H01L27/0207 , H01L27/0255 , H01L27/0296 , H01L27/0676 , H01L28/20 , H01L29/861 , H01L2924/0002 , H01L2924/00
Abstract: Described is an apparatus comprising: an input pad; an output pad; a wire, coupled to the input pad and the output pad, the wire positioned at a periphery of a semiconductor die, the wire extending substantially along a perimeter of the semiconductor die; and one or more diodes, coupled at various sections of the wire, and positioned along the perimeter of the semiconductor die and surrounding the semiconductor die.
Abstract translation: 描述了一种装置,包括:输入垫; 输出板 电线,其耦合到所述输入焊盘和所述输出焊盘,所述导线定位在半导体管芯的周围,所述焊丝基本上沿着所述半导体管芯的周边延伸; 以及一个或多个二极管,其耦合在所述导线的各个部分处,并且沿着所述半导体管芯的周边定位并围绕所述半导体管芯。
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公开(公告)号:US11226353B2
公开(公告)日:2022-01-18
申请号:US16493503
申请日:2017-03-31
Applicant: Intel Corporation
Inventor: Chengqing Hu , Mayue Xie , Simranjit S. Khalsa , Deepak Goyal
Abstract: An electrical characterization and fault isolation probe can include a cable, a connector, and a coating over a portion of the cable. The cable can have a first conductor having a first impedance, a second conductor having a second impedance, and a dielectric surrounding the first conductor and electrically isolating the first conductor from the second conductor. The connector can physically couple to, and be in electrical communication with, the cable. The connector can include a first electrical communication pathway and a second electrical communication pathway. The first electrical communication pathway can be electrically isolated from the second electrical communication pathway. The first electrical communication pathway can be in electrical communication with the first conductor. The second electrical communication pathway can be in electrical communication with the second conductor. The connector can have a fifth impedance.
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公开(公告)号:US20210132113A1
公开(公告)日:2021-05-06
申请号:US16493503
申请日:2017-03-31
Applicant: Intel Corporation
Inventor: Chengqing Hu , Mayue Xie , Simranjit S. Khalsa , Deepak Goyal
Abstract: An electrical characterization and fault isolation probe can include a cable, a connector, and a coating over a portion of the cable. The cable can have a first conductor having a first impedance, a second conductor having a second impedance, and a dielectric surrounding the first conductor and electrically isolating the first conductor from the second conductor. The connector can physically couple to, and be in electrical communication with, the cable. The connector can include a first electrical communication pathway and a second electrical communication pathway. The first electrical communication pathway can be electrically isolated from the second electrical communication pathway. The first electrical communication pathway can be in electrical communication with the first conductor. The second electrical communication pathway can be in electrical communication with the second conductor. The connector can have a fifth impedance.
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公开(公告)号:US20170141006A1
公开(公告)日:2017-05-18
申请号:US15421338
申请日:2017-01-31
Applicant: INTEL CORPORATION
Inventor: Mayue Xie , Zhiyong Wang , Yuan-Chuan Steven Chen
CPC classification number: H01L22/34 , G01R31/2642 , H01L22/32 , H01L23/48 , H01L23/50 , H01L27/0207 , H01L27/0255 , H01L27/0296 , H01L27/0676 , H01L28/20 , H01L29/861 , H01L2924/0002 , H01L2924/00
Abstract: Described is an apparatus comprising: an input pad; an output pad; a wire, coupled to the input pad and the output pad, the wire positioned at a periphery of a semiconductor die, the wire extending substantially along a perimeter of the semiconductor die; and one or more diodes, coupled at various sections of the wire, and positioned along the perimeter of the semiconductor die and surrounding the semiconductor die.
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公开(公告)号:US20180335465A1
公开(公告)日:2018-11-22
申请号:US15776979
申请日:2015-11-18
Applicant: Intel Corporation
Inventor: Mayue Xie , Simranjit S. Khalsa , Hemachandar Tanukonda Devarajulu , Deepak Goyal , Zhiguo Qian
CPC classification number: G01R31/11 , G01R31/2853 , G01R31/2896 , G01R31/311
Abstract: An apparatus comprises a signal generator circuit, a test probe, a signal sensor circuit, and a defect detection circuit. The signal generator circuit is configured to generate an impulse test signal having an impulse waveform and adjust a bandwidth of the impulse test signal. The test probe is electrically coupled to the signal generator circuit and configured to apply the impulse test signal to a device under test (DUT). The signal sensor circuit is configured to sense a conducted test signal produced by applying the impulse test signal to the DUT with the test probe. The defect detection circuit is configured to generate an indication of a defect in the DUT using the conducted test signal.
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公开(公告)号:US20180284185A1
公开(公告)日:2018-10-04
申请号:US15474674
申请日:2017-03-30
Applicant: Intel Corporation
Inventor: Mayue Xie , Zhiguo Qian , Jong-Ru Guo , Zhichao Zhang , Zuoguo Wu
IPC: G01R31/28
Abstract: A die with a transmission circuit, a reception circuit, and a comparison circuit can be provided. The transmission circuit can be configured to transmit a first signal through a first channel at a first transmission rate and a first transmission amplitude. The reception circuit can be in communication with the transmission circuit through the first channel. The reception circuit can receive a second signal at a first reception rate and at a first reception amplitude. The comparison circuit can be in communication with the transmission circuit and the reception circuit. The comparison circuit can be configured to: determine a first rate error value, determine a first amplitude error value, compare the first rate error value with a rate threshold to determine a first rate error occurrence, and compare the first amplitude error value with an amplitude threshold to determine a first amplitude error occurrence.
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公开(公告)号:US09159646B2
公开(公告)日:2015-10-13
申请号:US13713935
申请日:2012-12-13
Applicant: Intel Corporation
Inventor: Mayue Xie , Zhiyong Wang , Yuan-Chuan Steven Chen
CPC classification number: H01L22/34 , G01R31/2642 , H01L22/32 , H01L23/48 , H01L23/50 , H01L27/0207 , H01L27/0255 , H01L27/0296 , H01L27/0676 , H01L28/20 , H01L29/861 , H01L2924/0002 , H01L2924/00
Abstract: Described is an apparatus comprising: an input pad; an output pad; a wire, coupled to the input pad and the output pad, the wire positioned at a periphery of a semiconductor die, the wire extending substantially along a perimeter of the semiconductor die; and one or more diodes, coupled at various sections of the wire, and positioned along the perimeter of the semiconductor die and surrounding the semiconductor die.
Abstract translation: 描述了一种装置,包括:输入垫; 输出板 电线,其耦合到所述输入焊盘和所述输出焊盘,所述导线定位在半导体管芯的周围,所述焊丝基本上沿着所述半导体管芯的周边延伸; 以及一个或多个二极管,其耦合在所述导线的各个部分处,并且沿着所述半导体管芯的周边定位并围绕所述半导体管芯。
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公开(公告)号:US11450613B2
公开(公告)日:2022-09-20
申请号:US15933934
申请日:2018-03-23
Applicant: Intel Corporation
Inventor: Mayue Xie , Jong-Ru Guo , Zhiguo Qian , Zuoguo Wu
IPC: H01L23/538 , H01L25/065 , H01L23/58 , G01R31/28
Abstract: Apparatuses, systems and methods associated with integrated circuit packages with integrated test circuitry for testing of a channel between dies are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first die, a second die, and a channel that couples the first die to the second die. The first die may include a transmitter, test circuitry coupled between the transmitter and the channel, wherein the test circuitry is to control charge and discharge of the channel, and a receiver coupled to the channel. The receiver may determine a voltage of the channel during charge and discharge of the channel, and output an indication of the voltage. Other embodiments may be described and/or claimed.
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公开(公告)号:US10935593B2
公开(公告)日:2021-03-02
申请号:US15857520
申请日:2017-12-28
Applicant: Intel Corporation
Inventor: Deepak Goyal , Mayue Xie , Sivaseetharaman Pandi
Abstract: A method, system and computer readable medium for determination of distance to an electrical fault within a device. A signal generator excites the device with an electrical input signal. The device comprises an open circuited electrical transmission line. A frequency domain analyzer analyzes part of the signal reflected from the device for determination of the locations of resonant frequency of the signal within the device. A computer calculates the distance to the fault within the device, based on the resonant frequency. The distance to the fault is one quarter wavelength distance into the device at the resonant frequency. A frequency sweeper sweeps the frequency of the input signal and repeated calculation of the distance to the fault made at a plurality of resonant frequencies during the frequency sweep confirms the distance to the fault by convergence of the result of the repeated calculations to substantially the same location.
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