中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.013 seconds)

    Glitch-free digitally controlled oscillator code update
    1.
    发明授权
    Glitch-free digitally controlled oscillator code update 有权
    无毛刺数字控制振荡器代码更新

    公开(公告)号：US09548747B2

    公开(公告)日：2017-01-17

    申请号：US14713174

    申请日：2015-05-15

    Applicant: Intel Corporation

    Inventor： Fangxing Wei ,  Michael J. Allen ,  Setul M. Shah

    IPC: H03L7/085 ,  H03L7/099 ,  H03L7/095 ,  H03L7/087

    CPC classification number: H03L7/0991 ,  H03L7/087 ,  H03L7/093 ,  H03L7/095 ,  H03L7/0995 ,  H03L2207/50

    Abstract: A glitch-free digitally controlled oscillator (DCO) code update may be achieved by synchronizing the transfer of the DCO code update to a logic state transition of a pulse in the DCO clock output signal such that the code update may be achieved while the DCO delay chain remains in the same logic state. A state machine may provide the DCO code update and a pulsed update signal to a timing circuit. The DCO code update may be aligned with a pulse in the pulsed update signal. The timing circuit may generate a DCO code update enabled signal upon alignment of the pulse in the pulsed update signal with a state transition of a pulse in the pulsed DCO clock output. The DCO code update enabled signal may be aligned with a state transition in the pulsed DCO clock output to permit a glitch-free DCO code update.

    Abstract translation: 可以通过将DCO代码更新的传送同步到DCO时钟输出信号中的脉冲的逻辑状态转换来实现无毛刺的数字控制振荡器（DCO）代码更新，使得可以在DCO延迟期间实现代码更新 链条保持在相同的逻辑状态。 状态机可以将DCO代码更新和脉冲更新信号提供给定时电路。 DCO代码更新可以与脉冲更新信号中的脉冲对准。 定时电路可以在脉冲更新信号中的脉冲与脉冲DCO时钟输出中的脉冲的状态转换对齐时产生DCO代码更新使能信号。 DCO代码更新使能信号可以与脉冲DCO时钟输出中的状态转换对齐，以允许无毛刺的DCO代码更新。

    DIGITAL PHASE CONTROL WITH PROGRAMMABLE TRACKING SLOPE
    2.
    发明申请
    DIGITAL PHASE CONTROL WITH PROGRAMMABLE TRACKING SLOPE 有权
    数字相位控制与可编程跟踪斜率

    公开(公告)号：US20160373119A1

    公开(公告)日：2016-12-22

    申请号：US14745326

    申请日：2015-06-19

    Applicant: Intel Corporation

    Inventor： Fangxing Wei ,  Setul M. Shah ,  Michael J. Allen ,  Khushal N. Chandan

    IPC: H03L7/081 ,  G11C7/10

    CPC classification number: H03L7/0814 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/0818

    Abstract: Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for better tracking of environmental conditions. The phase compensation circuit can generate a linear code to apply phase compensation to lock phase of an I/O signal to a phase of a timing signal. The circuit selectively adjusts the linear code with a variable, programmable slope, where the slope defines how much phase compensation is applied per unit change in the linear code. The circuit applies the adjusted linear code to a lock loop to lock the phase of the I/O signal to the phase of the timing signal.

    Abstract translation: I / O（输入/输出）电路中的相位补偿包括可变的可编程斜率。 相位补偿电路可以对一个斜率进行相位补偿，并动态地改变相位补偿的斜率，以便更好地跟踪环境条件。 相位补偿电路可以产生线性码，以施加相位补偿，以将I / O信号的相位锁定到定时信号的相位。 电路用可变的可编程斜率选择性地调整线性代码，其中斜率定义了线性代码中每单位变化所施加的相位补偿量。 该电路将调整后的线性码应用于锁定环路，以将I / O信号的相位锁定到定时信号的相位。

    Phase detector in a delay locked loop
    4.
    发明授权
    Phase detector in a delay locked loop 有权

    公开(公告)号：US10122526B2

    公开(公告)日：2018-11-06

    申请号：US15477078

    申请日：2017-04-01

    Applicant: Intel Corporation

    Inventor： Fangxing Wei ,  Dan Shi ,  Michael J. Allen

    IPC: H04L7/033 ,  H04L7/027 ,  H04L7/04 ,  H03L7/087 ,  H04L7/00

    Abstract: Technology for a phase detector is described. The phase detector can include a reference clock. The phase detector can include a feedback clock. The phase detector can include a first latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock. The phase detector can include a second latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state. The phase detector can include a third latch that loads the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in a low state.

Patent Agency Ranking