公开(公告)号：US20220157799A1

公开(公告)日：2022-05-19

申请号：US17587664

申请日：2022-01-28

Applicant: Intel Corporation

Inventor： Russell K. MORTENSEN ,  Robert M. NICKERSON ,  Nicholas R. WATTS

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H05K1/11 ,  H05K3/40 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US20240006401A1

公开(公告)日：2024-01-04

申请号：US18368424

申请日：2023-09-14

Applicant: Intel Corporation

Inventor： Russell K. MORTENSEN ,  Robert M. NICKERSON ,  Nicholas R. WATTS

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H05K1/11 ,  H05K3/40 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/105 ,  H05K1/113 ,  H05K3/4038 ,  H01L23/49833 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L25/50 ,  H01L25/0657 ,  Y10T29/49124 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/32225 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16146 ,  H01L24/32 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L24/48 ,  H01L2224/16238 ,  H01L2224/73265 ,  H01L24/16 ,  H01L2225/1058 ,  H01L2224/13025 ,  H01L2924/15331 ,  H01L2224/32145 ,  H01L2224/0557 ,  H01L2224/0401 ,  H01L2924/00014 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/08238 ,  H01L2224/16227 ,  H01L2224/48245 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1511 ,  H01L2924/15321 ,  H01L2924/381 ,  H01L2224/48106 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2924/143 ,  H01L2924/1434

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US20240222350A1

公开(公告)日：2024-07-04

申请号：US18610104

申请日：2024-03-19

Applicant: Intel Corporation

Inventor： Russell K. MORTENSEN ,  Robert M. NICKERSON ,  Nicholas R. WATTS

IPC: H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H05K1/11 ,  H05K3/40

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H05K1/113 ,  H05K3/4038 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/08238 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/143 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1511 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/381 ,  Y10T29/49124

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US20220344318A1

公开(公告)日：2022-10-27

申请号：US17855664

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Russell K. MORTENSEN ,  Robert M. Nickerson ,  Nicholas R. Watts

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H05K1/11 ,  H05K3/40 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.