公开(公告)号：US20240103065A1

公开(公告)日：2024-03-28

申请号：US17954107

申请日：2022-09-27

Applicant: International Business Machines Corporation

Inventor： Arvind Kumar ,  Ramachandra Divakaruni ,  Mukta Ghate Farooq ,  John W. Golz ,  JIN PING HAN ,  Mounir Meghelli

IPC: G01R31/28 ,  G01R31/3187 ,  G06F13/40

CPC classification number: G01R31/2843 ,  G01R31/3187 ,  G06F13/4027 ,  G06F13/4068

Abstract: A semiconductor integrated circuit device includes: an active bridge; a first chiplet and a second chiplet mounted onto the active bridge; and a short-to-long converter circuit (SLCC) that has analog and digital portions. The active bridge includes at least the analog portion of the SLCC, which is electrically connected to at least the first chiplet; and a short-reach physical layer that electrically connects the first chiplet and the second chiplet. The first chiplet includes a first logic core; a first chiplet interface that is electrically connected between the first logic core and the SLCC; and a second chiplet interface that is electrically connected between the first logic core and the second chiplet. The second chiplet includes a second logic core; and a third chiplet interface that is electrically connected between the second logic core and the second chiplet interface. The active bridge also can include a built-in-self-test (BIST) circuit.

公开(公告)号：US20210020529A1

公开(公告)日：2021-01-21

申请号：US16517568

申请日：2019-07-20

Applicant: International Business Machines Corporation

Inventor： Dale Curtis McHerron ,  Kamal K. Sikka ,  Joshua M. Rubin ,  Ravi K. Bonam ,  Ramachandra Divakaruni ,  William J. Starke ,  Maryse Courmoyer

IPC: H01L23/13 ,  H01L23/538 ,  H01L23/532 ,  H01L27/24

Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips. Arrays of MCMs and methods of making bridge connects are disclosed. Bridge connector shapes include: rectangular, window pane, plus-shaped, circular shaped, and polygonal-shaped.

公开(公告)号：US10586799B2

公开(公告)日：2020-03-10

申请号：US16012951

申请日：2018-06-20

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni

IPC: H01L27/112 ,  H01L23/525 ,  H01L23/00

Abstract: A method for forming a semiconductor device includes forming a nanosheet stack comprising alternating layers of a first material and a second material on a substrate. The method further includes removing portions of the stack to form tapered stack sidewalls, which have a taper angle in relation to a horizontal surface of the substrate. The method further includes converting the second material to a resistive material. The layers that include the resistive material form one or more electrical fuses.

公开(公告)号：US20200043811A1

公开(公告)日：2020-02-06

申请号：US16598517

申请日：2019-10-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jeehwan Kim ,  Juntao Li ,  Devendra K. Sadana

IPC: H01L21/84 ,  H01L27/12 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L29/167 ,  H01L21/326 ,  H01L21/265 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78

Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

公开(公告)号：US20190189761A1

公开(公告)日：2019-06-20

申请号：US16278917

申请日：2019-02-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L21/768 ,  H01L21/265 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L23/535 ,  H01L29/49

CPC classification number: H01L29/41783 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76243 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/7834

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a bilayer buried insulator over a substrate, forming an extremely thin silicon-on-insulator (ETSOI) over the bilayer buried insulator, forming a dummy gate, and forming a source/drain next to the dummy gate, the source/drain defining a raised source/drain region. The method further includes depositing a dielectric material over the raised source/drain regions, removing the dummy gate to define a recess, implanting a species within a first layer of the bilayer buried insulator, and depositing a gate dielectric and a conducting material within the recess. The method further includes removing the substrate, etching the implanted portion of the first layer of the bilayer buried insulator to expose a surface of a second layer of the bilayer buried insulator, and forming a back gate over the exposed second layer, the back gate self-aligned to the ETSOI channel.

公开(公告)号：US20180269220A1

公开(公告)日：2018-09-20

申请号：US15988828

申请日：2018-05-24

Applicant: International Business Machines Corporation

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl J. Radens

IPC: H01L27/11568 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/12 ,  H01L21/28 ,  H01L29/792 ,  H01L29/40 ,  H01L27/088

CPC classification number: H01L27/11568 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1203 ,  H01L29/40117 ,  H01L29/408 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: A plurality of fin structures containing, from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of a first conductivity type, extend upwards from a surface of a first doped semiconductor portion of the first conductivity type. A trapping material (e.g., an electron-trapping material) is present along a bottom portion of sidewall surfaces of each non-doped semiconductor portion and on exposed portions of each first doped semiconductor portion. Functional gate structures straddle each fin structure. Metal lines are located above each fin structure and straddle each functional gate structure. Each metal line is orientated perpendicular to each functional gate structure and has a bottommost surface that is in direct physical contact with a portion of a topmost surface of each of the second doped semiconductor portions.

公开(公告)号：US10002876B2

公开(公告)日：2018-06-19

申请号：US14527256

申请日：2014-10-29

Applicant: International Business Machines Corporation

Inventor： Ramachandra Divakaruni ,  Arvind Kumar ,  Carl J. Radens

IPC: H01L21/8242 ,  H01L27/11568 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/12 ,  H01L29/40 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1203 ,  H01L29/40117 ,  H01L29/408 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: A plurality of fin structures containing, from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of a first conductivity type, extend upwards from a surface of a first doped semiconductor portion of the first conductivity type. A trapping material (e.g., an electron-trapping material) is present along a bottom portion of sidewall surfaces of each non-doped semiconductor portion and on exposed portions of each first doped semiconductor portion. Functional gate structures straddle each fin structure. Metal lines are located above each fin structure and straddle each functional gate structure. Each metal line is orientated perpendicular to each functional gate structure and has a bottommost surface that is in direct physical contact with a portion of a topmost surface of each of the second doped semiconductor portions.

公开(公告)号：US09997606B2

公开(公告)日：2018-06-12

申请号：US15282349

申请日：2016-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni

IPC: H01L29/417 ,  H01L23/535 ,  H01L29/06 ,  H01L21/265 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L29/41783 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76243 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/78

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a bilayer buried insulator over a substrate, forming an extremely thin silicon-on-insulator (ETSOI) over the bilayer buried insulator, forming a dummy gate, and forming a source/drain next to the dummy gate, the source/drain defining a raised source/drain region. The method further includes depositing a dielectric material over the raised source/drain regions, removing the dummy gate to define a recess, implanting a species within a first layer of the bilayer buried insulator, and depositing a gate dielectric and a conducting material within the recess. The method further includes removing the substrate, etching the implanted portion of the first layer of the bilayer buried insulator to expose a surface of a second layer of the bilayer buried insulator, and forming a back gate over the exposed second layer, the back gate self-aligned to the ETSOI channel.

公开(公告)号：US20180114865A1

公开(公告)日：2018-04-26

申请号：US15840122

申请日：2017-12-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni

IPC: H01L29/786 ,  H01L21/84 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78684

Abstract: A method for forming a semiconductor device includes etching a semiconductor layer using a gate structure and spacers as a mask to protect portions of the semiconductor layer that extend beyond the gate structure. Undercuts are formed in a buried dielectric layer under the gate structure. Source and drain regions are epitaxially growing and wrapped around the semiconductor layer by forming the source and drain regions adjacent to the gate structure on a first side of the semiconductor layer and in the undercuts on a second side of the semiconductor layer opposite the first side.

公开(公告)号：US20180108751A1

公开(公告)日：2018-04-19

申请号：US15835526

申请日：2017-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Juntao Li ,  Xin Miao

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/6681 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7853

Abstract: Transistors include stress liners, with one or more semiconductor structures between the stress liners. The stress liners provide a stress on the one or more semiconductor structures. A gate is formed over and around the one or more semiconductor structures. A source and drain region is formed on the one or more semiconductor structures on opposite sides of the gate, between the stress liners.