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    DAMASCENE METHOD FOR IMPROVED MOS TRANSISTOR
    2.
    发明申请
    DAMASCENE METHOD FOR IMPROVED MOS TRANSISTOR 失效
    改进的MOS晶体管的改进方法

    公开(公告)号：US20040135212A1

    公开(公告)日：2004-07-15

    申请号：US10342423

    申请日：2003-01-14

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens

    IPC分类号： H01L021/336

    CPC分类号： H01L29/66583 ,  H01L21/26586 ,  H01L21/28114 ,  H01L29/665 ,  H01L29/66553

    摘要： A MOSFET fabrication methodology and device structure, exhibiting improved gate activation characteristics. The gate doping that may be introduced while the source drain regions are protected by a damascene mandrel to allow for a very high doping in the gate conductors, without excessively forming deep source/drain diffusions. The high gate conductor doping minimizes the effects of electrical depletion of carriers in the gate conductor. The MOSFET fabrication methodology and device structure further results in a device having a lower gate conductor width less than the minimum lithographic minimum image, and a wider upper gate conductor portion width which may be greater than the minimum lithographic image. Since the effective channel length of the MOSFET is defined by the length of the lower gate portion, and the line resistance is determined by the width of the upper gate portion, both short channel performance and low gate resistance are satisfied simultaneously.

    摘要翻译： MOSFET制造方法和器件结构，表现出改进的栅极激活特性。 当源极漏极区域被镶嵌心轴保护以允许栅极导体中的非常高的掺杂而不会过度地形成深的源极/漏极扩散时，可以引入栅极掺杂。 高栅极导体掺杂最大限度地减小了栅极导体中载流子的电耗损的影响。 MOSFET制造方法和器件结构进一步导致具有小于最小光刻最小图像的较低栅极导体宽度的器件，以及可能大于最小光刻图像的较宽上部栅极导体部分宽度。 由于MOSFET的有效沟道长度由下栅极部分的长度限定，并且线路电阻由上部栅极部分的宽度决定，所以同时满足短沟道性能和低栅极电阻。

    Isolation structures for imposing stress patterns
    4.
    发明申请
    Isolation structures for imposing stress patterns 有权
    施加应力模式的隔离结构

    公开(公告)号：US20040113174A1

    公开(公告)日：2004-06-17

    申请号：US10318600

    申请日：2002-12-12

    申请人： International Business Machines Corporation

    发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Jack A. Mandelman

    IPC分类号： H01L031/109

    CPC分类号： H01L29/7846 ,  H01L21/76232 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/785

    摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.

    摘要翻译： 在张力和/或压缩下的基底改善了在其中制造的器件的性能。 可以通过选择适当的STI填充材料将张力和/或压缩施加在基底上。 STI区域形成在衬底层中并且在相邻衬底区域上施加力。 在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。 通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，实现了IC性能的提高。

    ANTI-SPACER STRUCTURE FOR SELF-ALIGNED INDEPENDENT GATE IMPLANTATION
    5.
    发明申请
    ANTI-SPACER STRUCTURE FOR SELF-ALIGNED INDEPENDENT GATE IMPLANTATION 失效
    自对准独立门植入的防空间结构

    公开(公告)号：US20020197839A1

    公开(公告)日：2002-12-26

    申请号：US09888160

    申请日：2001-06-22

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Peter Smeys ,  Isabel Y. Yang

    IPC分类号： H01L021/8238 ,  H01L021/336 ,  H01L021/3205 ,  H01L021/4763

    CPC分类号： H01L21/82345

    摘要： A method for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a plurality of patterned gate stacks atop a layer of gate dielectric material; forming a first planarizing organic film on the gate dielectric material and abutting vertical sidewalls of the patterned gate stacks, said planarizing organic film not being present on top, horizontal surfaces of each of the patterned gate stacks; blocking some of the plurality of patterned gate stacks with a first resist, while leaving other patterned gate stacks of said plurality unblocked; implanting first ions into the unblocked patterned gate stacks; removing the first resist and first planarizing organic film and forming a second planarizing organic film and blocking the previously unblocked patterned gate stacks with a second resist; implanting second ions into the patterned gate stacks that are not blocked by said second resist; and removing the second resist and the second planarizing organic film.

    摘要翻译： 提供了一种用于改善金属氧化物半导体场效应晶体管（MOSFET）结构的栅激活的方法。 本发明的方法包括以下步骤：在栅极电介质材料层的上方形成多个图案化的栅叠层; 在所述栅极电介质材料上形成第一平面化有机膜并邻接所述图案化栅极叠层的垂直侧壁，所述平面化有机膜不存在于每个所述图案化栅极堆叠的顶部水平表面上; 用第一抗蚀剂阻挡多个图案化栅极堆叠中的一些，同时留下所述多个未封装的其它图案化栅极堆叠; 将第一离子注入未封闭的图案化栅极堆叠中; 去除第一抗蚀剂和第一平面化有机膜并形成第二平面化有机膜并用第二抗蚀剂阻挡先前未封闭的图案化栅叠层; 将第二离子注入未被所述第二抗蚀剂阻挡的图案化栅极堆叠中; 并除去第二抗蚀剂和第二平面化有机膜。

    Structure and method to preserve STI during etching
    6.
    发明申请
    Structure and method to preserve STI during etching 有权
    蚀刻期间保留STI的结构和方法

    公开(公告)号：US20020175146A1

    公开(公告)日：2002-11-28

    申请号：US09864974

    申请日：2001-05-24

    申请人： International Business Machines Corporation

    发明人： Omer H. Dokumaci ,  Bruce B. Doris

    IPC分类号： B44C001/22 ,  C23F001/00 ,  C03C015/00

    CPC分类号： H01L21/31144 ,  H01L21/3185 ,  H01L21/76224 ,  H01L21/76283

    摘要： Disclosed is a method of protecting a semiconductor shallow trench isolation (STI) oxide from etching, the method comprising lowering, if necessary, the upper surface of said STI oxide to a level below that of adjacent silicon active areas, depositing a nitride liner upon said STI oxide and adjacent silicon active areas in a manner effective in defining a depression above said STI oxide, filling said depression with a protective film, and removing said nitride layer from said adjacent active areas.

    摘要翻译： 公开了一种保护半导体浅沟槽隔离（STI）氧化物免受蚀刻的方法，所述方法包括如果需要，将所述STI氧化物的上表面降低至低于相邻硅有源区的上表面，将氮化物衬垫沉积在所述 STI氧化物和相邻的硅有源区，以有效地限定所述STI氧化物上方的凹陷的方式，用保护膜填充所述凹陷，以及从所述相邻的活性区域移除所述氮化物层。

    MOS TRANSISTOR
    8.
    发明申请
    MOS TRANSISTOR 有权
    MOS晶体管

    公开(公告)号：US20040132236A1

    公开(公告)日：2004-07-08

    申请号：US10338930

    申请日：2003-01-08

    申请人： International Business Machines Corporation

    发明人： Bruce B. Doris ,  Omer H. Dokumaci ,  Jack A. Mandelman ,  Carl J. Radens

    IPC分类号： H01L021/338

    CPC分类号： H01L21/28114 ,  H01L21/26586 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/665

    摘要： A method of fabricating a semiconductor transistor device comprises the steps as follows. Provide a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed over the gate dielectric layer with the lower gate electrode structure having a lower gate top. Form a planarizing layer over the gate dielectric layer leaving the gate top of the lower gate electrode structure exposed. Form an upper gate structure over the lower gate electrode structure to form a T-shaped gate electrode with an exposed lower surface of the upper gate surface and exposed vertical sidewalls of the gate electrode. Remove the planarizing layer. Form source/drain extensions in the substrate protected from the short channel effect. Form sidewall spacers adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewalls of the T-shaped gate electrode. Form source/drain regions in the substrate. Form silicide layers on top of the T-shaped gate electrode and above the source/drain regions.

    摘要翻译： 制造半导体晶体管器件的方法包括以下步骤。 提供其上具有栅极介电层的半导体衬底和形成在栅极电介质层上的下部栅极电极结构，而下部栅电极结构具有较低的栅极顶部。 在栅极电介质层上形成平坦化层，离开下部栅电极结构的栅极顶部。 在下栅极电极结构上形成上栅极结构，形成具有上栅极表面的暴露下表面和暴露的栅电极垂直侧壁的T形栅电极。 取出平坦化层。 衬底中形成源/漏极扩展，防止短沟道效应。 形成邻近上部栅极的暴露的下表面和T形栅电极的暴露的垂直侧壁的侧壁间隔物。 在衬底中形成源/漏区。 在T形栅电极的顶部和源极/漏极区之上形成硅化物层。