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公开(公告)号：US20020197807A1
公开(公告)日：2002-12-26
申请号：US09885792
申请日：2001-06-20
发明人： Basanth Jagannathan , Shwu-Jen Jeng , Jeffrey B. Johnson , Robb A. Johnson , Louis D. Lanzerotti , Kenneth J. Stein , Seshadri Subbanna
IPC分类号： H01L021/331 , H01L021/8222
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/7378
摘要： A method for making a non-self-aligned, heterojunction bipolar transistor includes forming extrinsic base regions with a PFET source/drain implant aligned with the polysilicon in an emitter stack but which are not directly aligned with an emitter opening defined in that stack. This is achieved by making the emitter pedestal wider than the emitter opening. This advantageously removes the dependency of alignment between the extrinsic base regions and the emitter opening, thereby resulting in fewer process steps, reduced thermal cycles, and improved speed.
摘要翻译： 用于制造非自对准异质结双极晶体管的方法包括：在发射极堆叠中与多晶硅对准的PFET源极/漏极注入形成非本征基极区域，但不直接对准在该叠层中限定的发射极开口。 这通过使发射器基座宽于发射器开口来实现。 这有利地消除了非本征基区和发射极开口之间的对准的依赖性，从而导致更少的工艺步骤，减少的热循环和改进的速度。
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公开(公告)号：US20040097003A1
公开(公告)日：2004-05-20
申请号：US10300520
申请日：2002-11-20
IPC分类号： H01L021/00 , H01L021/44
CPC分类号： B81C1/00666 , B81B2201/014 , B81C2201/0167 , H01F2007/068 , H01H50/005
摘要： A method of fabricating an encapsulated micro electro-mechanical system (MEMS) and making of same that includes forming a dielectric layer, patterning an upper surface of the dielectric layer to form a trench, forming a release material within the trench, patterning an upper surface of the release material to form another trench, forming a first encapsulating layer that includes sidewalls within the another trench, forming a core layer within the first encapsulating layer, and forming a second encapsulating layer above the core layer, where the second encapsulating layer is connected to the sidewalls of the first encapsulating layer. Alternatively, the method includes forming a multilayer MEMS structure by photomasking processes to form a first metal layer, a second layer including a dielectric layer and a second metal layer, and a third metal layer. The core layer and the encapsulating layers are made of materials with complementary electrical, mechanical and/or magnetic properties.
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3.发明申请公开(公告)号：US20030059992A1
公开(公告)日：2003-03-27
申请号：US09961009
申请日：2001-09-21
IPC分类号： H01L021/337
CPC分类号： H01L28/24 , H01C17/262
摘要： A method of improving the tolerance of a back-end-of-the-line (BEOL) thin film resistor is provided. Specifically, the method of the present invention includes an anodization step which is capable of converting a portion of base resistor film into an anodized region. The anodized resistor thus formed has a sheet resistivity that is higher than that of the base resistor film.
摘要翻译： 提供了一种改进后端（BEOL）薄膜电阻的公差的方法。 具体地，本发明的方法包括能够将基极电阻膜的一部分转变为阳极氧化区域的阳极氧化步骤。 如此形成的阳极氧化电阻的电阻率比基极电阻膜高。
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4.发明申请Method of fabricating a polysilicon capacitor utilizing FET and bipolar base polysilicon layers 失效使用FET和双极基极多晶硅层制造多晶硅电容器的方法公开(公告)号：US20030141534A1
公开(公告)日：2003-07-31
申请号：US10339151
申请日：2003-01-09
IPC分类号： H01L027/108
CPC分类号： H01L28/40 , H01L21/8249 , H01L27/0635 , Y10S438/951
摘要： A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.
摘要翻译： 一种在衬底上同时形成多晶硅多晶硅电容器，MOS晶体管和双极晶体管的方法，包括以下步骤：在衬底上沉积和构图第一层多晶硅以形成所述电容器的第一平板电极和电极 并且在衬底上沉积和构图第二层多晶硅以形成所述电容器的第二平板电极和双极晶体管的电极。
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5.发明申请Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling 失效用于双极晶体管和相关工具的低缺陷预发射极和预基底氧化物蚀刻公开(公告)号：US20040110354A1
公开(公告)日：2004-06-10
申请号：US10316211
申请日：2002-12-10
发明人： Wesley C. Natzle , David C. Ahlgren , Steven G. Barbee , Marc W. Cantell , Basanth Jagannathan , Louis D. Lanzerotti , Seshadri Subbanna , Ryan W. Wuthrich
IPC分类号： H01L021/331 , H01L021/8222
CPC分类号： H01L29/66242 , H01L21/31116 , H01L21/8249
摘要： An oxide etch process is described which may be used for emitter and base preparation in bipolar SiGe devices. The low temperature process employed produces electrical insulation between the emitter and base by a COR etch which preserves insulating TEOS glass. The insulating TEOS glass provides reduced capacitance and helps to achieve high speed. An apparatus is also described for practicing the disclosed process.
摘要翻译： 描述了氧化物蚀刻工艺，其可用于双极SiGe器件中的发射极和基极准备。 所采用的低温工艺通过保留绝缘TEOS玻璃的COR蚀刻产生发射极和基极之间的电绝缘。 绝缘TEOS玻璃提供降低的电容并有助于实现高速度。 还描述了用于实施所公开的方法的装置。
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6.发明申请METHOD OF FABRICATING MICRO-ELECTROMECHANICAL SWITCHES ON CMOS COMPATIBLE SUBSTRATES 有权在CMOS兼容基板上制作微电子开关的方法公开(公告)号：US20030148550A1
公开(公告)日：2003-08-07
申请号：US10014660
申请日：2001-11-07
发明人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
IPC分类号： H01L021/00
CPC分类号： B81C1/00246 , B81B2201/016 , B81B2201/018 , B81B2203/0127 , B81B2207/07 , B81C1/00611 , B81C2201/0122 , B81C2203/0735 , H01G5/40 , H01H59/0009
摘要： A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.
摘要翻译： 描述了使用兼容工艺和材料制造与常规半导体互连级别集成的微机电开关（MEMS）的方法。 该方法基于制造容易修改以产生用于接触切换和任何数量的金属 - 介电金属开关的各种配置的电容开关。 该过程开始于铜镶嵌互连层，由金属导体嵌入电介质中。 铜互连的全部或部分凹陷到足以在开关处于闭合状态时提供电容气隙的程度，并为例如Ta / TaN的保护层提供空间。 在为开关指定的区域内限定的金属结构用作致动器电极以下拉可移动光束并且提供一个或多个路径用于开关信号横越。 气隙的优点是空气不会受到可能导致可靠性和电压漂移问题的电荷储存或捕集。 代替使电极凹陷以提供间隙，可以仅在电极上或周围添加电介质。 下一层是另一介质层，其被沉积到形成在下电极和形成开关器件的可移动梁之间的间隙的期望厚度上。 通过该电介质制造通孔以提供金属互连层和还包含可切换光束的下一个金属层之间的连接。 然后对通孔层进行图案化和蚀刻以提供包含下部激活电极以及信号路径的空腔区域。 然后用牺牲脱模材料填充空腔。 然后将该释放材料与电介质的顶部平坦化，由此提供构造波束层的平坦表面。
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公开(公告)号：US20030116850A1
公开(公告)日：2003-06-26
申请号：US10026146
申请日：2001-12-21
发明人： Richard P. Volant , Seshadri Subbanna , Robert A. Groves , John C. Malinowski , Kenneth J. Stein , Kevin S. Petrarca
IPC分类号： H01L023/48
CPC分类号： H01L23/66 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A passive electrical device includes a first electrical conductor, a second electrical conductor disposed over the first conductor; and a third electrical conductor connecting the first conductor to the second conductor. The said first, second and third conductors are disposed on a semiconductor substrate. The sheet resistivity of the first conductor is approximately equal to the sheet resistivity of the second conductor.
摘要翻译： 无源电气装置包括第一电导体，布置在第一导体上的第二电导体; 以及将第一导体连接到第二导体的第三电导体。 所述第一，第二和第三导体设置在半导体衬底上。 第一导体的薄层电阻率近似等于第二导体的薄层电阻率。
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8.发明申请Bipolar device having shallow junction raised extrinsic base and method for making the same 失效具有浅结的双极器件提出外在基极及其制造方法公开(公告)号：US20030057458A1
公开(公告)日：2003-03-27
申请号：US09962738
申请日：2001-09-25
发明人： Gregory G. Freeman , Seshadri Subbanna , Basanth Jagannathan , Kathryn T. Schonenberg , Shwu-Jen Jeng , Kenneth J. Stein , Jeffrey B. Johnson
IPC分类号： H01L029/80 , H01L031/112
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/7378
摘要： A raised extrinsic base, silicon germanium (SiGe) heterojunction bipolar transistor (HBT), and a method of making the same is disclosed herein. The heterojunction bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a raised extrinsic base layer formed on the silicon germanium layer, and an emitter layer formed on the silicon germanium layer. The silicon germanium layer forms a heterojunction between the emitter layer and the raised extrinsic base layer. The bipolar transistor further includes a base electrode formed on a portion of the raised extrinsic base layer, a collector electrode formed on a portion of the collector layer, and an emitter electrode formed on a portion of the emitter layer. Thus, the heterojunction bipolar transistor includes a self-aligned raised extrinsic base, a minimal junction depth, and minimal interstitial defects influencing the base width, all being formed with minimal thermal processing. The heterojunction bipolar transistor simultaneously improves three factors that affect the speed and performance of bipolar transistors: base width, base resistance, and base-collector capacitance.
摘要翻译： 本文公开了一种凸起的外在基极，硅锗（SiGe）异质结双极晶体管（HBT）及其制造方法。 异质结双极晶体管包括基板，形成在基板上的硅锗层，形成在基板上的集电极层，形成在硅锗层上的升高的非本征基极层和形成在硅锗层上的发射极层。 硅锗层在发射极层和凸起的非本征基极层之间形成异质结。 双极晶体管还包括形成在凸起的非本征基极层的一部分上的基极，在集电极层的一部分上形成的集电极，以及形成在发射极层的一部分上的发射极。 因此，异质结双极晶体管包括自对准凸起的外在基极，最小结深度以及影响基底宽度的最小间隙缺陷，全部以最小的热处理形成。 异质结双极晶体管同时改善了影响双极晶体管速度和性能的三个因素：基极宽度，基极电阻和基极集电极电容。
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