公开(公告)号：US20040087135A1

公开(公告)日：2004-05-06

申请号：US10280283

申请日：2002-10-24

Applicant: International Business Machines Corporation

Inventor： Donald F. Canaperi ,  Timothy J. Dalton ,  Stephen M. Gates ,  Mahadevaiyer Krishnan ,  Satya V. Nitta ,  Sampath Purushothaman ,  Sean P.E. Smith

IPC: H01L021/4763

CPC classification number: H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure incorporates very low dielectric constant (k) insulators with copper wiring to achieve high performance interconnects. The wiring is supported by a relatively durable low k dielectric such as SiLk or SiO2 and a very low k and less robust gap fill dielectric is disposed in the remainder of the structure, so that the structure combines a durable layer for strength with a very low k dielectric for interconnect electrical performance.

Abstract translation: 一个结构包含非常低的介电常数（k）绝缘体与铜布线，以实现高性能互连。 布线由相对耐用的低k电介质（例如SiLk或SiO 2）支撑，并且在该结构的其余部分中设置非常低的k和较不牢固的间隙填充电介质，使得该结构将耐用层与强度非常低 k电介质用于互连电性能。

公开(公告)号：US20030100190A1

公开(公告)日：2003-05-29

申请号：US09994340

申请日：2001-11-26

Applicant: International Business Machines Corporation

Inventor： William J. Cote ,  Timothy J. Dalton ,  Prakash Chimanlal Dev ,  Daniel C. Edelstein ,  Scott D. Halle ,  Gill Yong Lee ,  Arpan P. Mahorowala

IPC: H01L021/461 ,  H01L021/302

CPC classification number: H01L21/76808 ,  H01L21/31633

Abstract: A process for forming a damascene structure includes depositing a bilayer comprising a first dielectric layer and a second dielectric layer onto a substrate, wherein the first layer has a dielectric constant higher than the second layer, and wherein the second layer is selected from a low k dielectric material comprising Si, C, O and H. The multi-step damascene structure is patterned into the dielectric bilayer using highly selective anisotropic reactive ion etching. Photoresist, polymers and post etch residues are removed from the substrate using a plasma ashing process without damaging the underlying dielectric layers.

公开(公告)号：US20030148550A1

公开(公告)日：2003-08-07

申请号：US10014660

申请日：2001-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Richard P. Volant ,  John C. Bisson ,  Donna R. Cote ,  Timothy J. Dalton ,  Robert A. Groves ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Seshadri Subbanna

IPC: H01L021/00

CPC classification number: B81C1/00246 ,  B81B2201/016 ,  B81B2201/018 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C1/00611 ,  B81C2201/0122 ,  B81C2203/0735 ,  H01G5/40 ,  H01H59/0009

Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

Abstract translation: 描述了使用兼容工艺和材料制造与常规半导体互连级别集成的微机电开关（MEMS）的方法。 该方法基于制造容易修改以产生用于接触切换和任何数量的金属 - 介电金属开关的各种配置的电容开关。 该过程开始于铜镶嵌互连层，由金属导体嵌入电介质中。 铜互连的全部或部分凹陷到足以在开关处于闭合状态时提供电容气隙的程度，并为例如Ta / TaN的保护层提供空间。 在为开关指定的区域内限定的金属结构用作致动器电极以下拉可移动光束并且提供一个或多个路径用于开关信号横越。 气隙的优点是空气不会受到可能导致可靠性和电压漂移问题的电荷储存或捕集。 代替使电极凹陷以提供间隙，可以仅在电极上或周围添加电介质。 下一层是另一介质层，其被沉积到形成在下电极和形成开关器件的可移动梁之间的间隙的期望厚度上。 通过该电介质制造通孔以提供金属互连层和还包含可切换光束的下一个金属层之间的连接。 然后对通孔层进行图案化和蚀刻以提供包含下部激活电极以及信号路径的空腔区域。 然后用牺牲脱模材料填充空腔。 然后将该释放材料与电介质的顶部平坦化，由此提供构造波束层的平坦表面。

公开(公告)号：US20030087043A1

公开(公告)日：2003-05-08

申请号：US10005861

申请日：2001-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel C. Edelstein ,  William J. Cote ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Gill Young Lee

IPC: C23C016/00

CPC classification number: C23C16/30 ,  C23C16/505

Abstract: A process of depositing a low k dielectric film on a substrate includes using plasma enhance chemical vapor deposition to deposit a hydrogenated oxidized silicon carbon film. The process includes flowing a precursor gas containing Si, C, H and an oxygen-providing gas into the PECVD chamber. The precursor gas and the oxygen-providing gas are substantially free from nitrogen. The oxygen-providing gas is selected from the group consisting of oxygen, carbon monoxide, carbon dioxide, ozone, water vapor and a combination of at least one of the foregoing.

Abstract translation: 在衬底上沉积低k电介质膜的工艺包括使用等离子体增强化学气相沉积来沉积氢化的氧化硅碳膜。 该方法包括使含有Si，C，H和氧供给气体的前体气体流入PECVD室。 前体气体和供氧气体基本上不含氮气。 供氧气体选自氧气，一氧化碳，二氧化碳，臭氧，水蒸汽以及前述的至少一种的组合。

公开(公告)号：US20040113278A1

公开(公告)日：2004-06-17

申请号：US10319032

申请日：2002-12-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy J. Dalton ,  Sanjit K. Das ,  Brett H. Engel ,  Brian W. Herbst ,  Habib Hichri ,  Bernd E. Kastenmeier ,  Kelly Malone ,  Jeffrey R. Marino ,  Arthur Martin ,  Vincent J. McGahay ,  Ian D. Melville ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant

IPC: H01L023/48

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.

公开(公告)号：US20030080393A1

公开(公告)日：2003-05-01

申请号：US10002447

申请日：2001-10-26

Applicant: International Business Machines Corporation

Inventor： Timothy J. Dalton ,  Kevin S. Petrarca ,  Richard P. Volant

IPC: H01L029/00

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A laser-programmable fuse structure for an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the fuse structure includes a conductive layer, the conductive layer completing a conductive path between wiring segments in a wiring layer. An organic material is encapsulated underneath the conductive layer, wherein the fuse structure is blown open by application of a beam of laser energy thereto.

Abstract translation: 公开了一种用于集成电路器件的激光可编程熔丝结构。 在本发明的示例性实施例中，熔丝结构包括导电层，导电层在布线层中的布线段之间完成导电路径。 有机材料被封装在导电层下面，其中通过向其施加激光能量而将熔丝结构吹开。

公开(公告)号：US20040262264A1

公开(公告)日：2004-12-30

申请号：US10605801

申请日：2003-10-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shaun B. Crawford ,  Timothy J. Dalton ,  Thomas B. Faure ,  Cuc K. Huynh ,  Michelle L. Steen ,  Thomas M. Wagner

IPC: B44C001/22 ,  C23F001/00 ,  G03F009/00 ,  C23F003/00

CPC classification number: C23F4/00 ,  G03F1/80 ,  H01L21/0332 ,  H01L21/32136

Abstract: A photomask is formed by depositing an opaque layer on a transparent substrate. A resist is formed on the opaque layer and selectively patterned to expose the portions of the opaque layer that are to be etched out. During the dry etching step, the photomask is exposed to an etchant gas mixture which exhibits a selectivity equal to or higher than 1.2:1 between the opaque layer and the resist layer. Due to the selectivity of the gas mixture, a thinner resist film can be used, thereby increasing resolution and accuracy of the opaque layer pattern. Also, due to reduced susceptibility to both a macro-loading effect and a pattern density effect, overetching of the resist and underetching of the opaque layer are significantly reduced, thereby achieving improved etching uniformity and consequently improved CD uniformity.

Abstract translation: 通过在透明基底上沉积不透明层而形成光掩模。 抗蚀剂形成在不透明层上并选择性地图案化以暴露待被蚀刻出的不透明层的部分。 在干蚀刻步骤期间，光掩模暴露于在不透明层和抗蚀剂层之间具有等于或高于1.2:1的选择性的蚀刻剂气体混合物。 由于气体混合物的选择性，可以使用更薄的抗蚀剂膜，从而提高不透明层图案的分辨率和精度。 此外，由于对宏观负载效应和图案密度效应的敏感性降低，抗蚀剂的过蚀刻和不透明层的去抛光显着降低，从而实现了改进的蚀刻均匀性并因此改善了CD均匀性。

公开(公告)号：US20040113279A1

公开(公告)日：2004-06-17

申请号：US10319967

申请日：2002-12-16

Applicant: International Business Machines Corporation

Inventor： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P.E. Smith ,  Wei-tsu Tseng

IPC: H01L023/48 ,  H01L023/52 ,  H01L021/4763

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

Abstract translation: 公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。 互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

公开(公告)号：US20030134505A1

公开(公告)日：2003-07-17

申请号：US10053288

申请日：2002-01-17

Applicant: International Business Machines Corporation

Inventor： Timothy J. Dalton ,  Minakshisundaran B. Anand ,  Michael D. Armacost ,  Shyng-Tsong Chen ,  Stephen M. Gates ,  Stephen E. Greco ,  Simon M. Karecki ,  Satyanarayana V. Nitta ,  Anna Karecki

IPC: H01L021/4763 ,  H01L021/44

CPC classification number: H01L21/76829 ,  H01L21/76811 ,  H01L21/76826

Abstract: A method is described for forming a metal pattern in a low-dielectric constant substrate. A hardmask is prepared which includes a low-k lower hardmask layer and a top hardmask layer. The top hardmask layer is a sacrificial layer with a thickness of about 200 null, preferably formed of a refractory nitride, and which serves as a stopping layer in a subsequent CMP metal removal process. The patterning is performed using resist layers. Oxidation damage to the lower hardmask layer is avoided by forming a protective layer in the hardmask, or by using a non-oxidizing resist strip process.

Abstract translation: 描述了在低介电常数衬底中形成金属图案的方法。 准备了一个硬掩模，其包括低k较低的硬掩模层和顶部硬掩模层。 顶部硬掩模层是厚度为约200埃的牺牲层，优选由耐火氮化物形成，并且在随后的CMP金属去除工艺中用作停止层。 使用抗蚀剂层进行图案化。 通过在硬掩模中形成保护层，或者通过使用非氧化抗蚀剂剥离工艺来避免对下部硬掩模层的氧化损伤。

公开(公告)号：US20030089962A1

公开(公告)日：2003-05-15

申请号：US09992344

申请日：2001-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC: H01L021/82 ,  H01L029/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

Abstract translation: 用于熔丝结构的方法和结构包括绝缘体层，穿过绝缘体层延伸到下面的布线层的多个熔丝电极，连接到电极的电镀熔丝元件和界面壁。 保险丝元件位于绝缘体的外部，并且在绝缘体和保险丝元件之间并置有间隙。 界面壁还包括第一侧壁，第二侧壁和内壁，其中内壁设置在间隙内。 熔丝电极彼此直径相对，并且熔丝元件垂直地设置在熔丝电极的上方。 保险丝元件是电镀，无电镀，或是超薄保险丝。