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    Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity
    1.
    发明申请
    Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity 有权
    深沟槽埋层阵列​​和用于噪声隔离和闭锁抗扰度的集成器件结构

    公开(公告)号：US20020084506A1

    公开(公告)日：2002-07-04

    申请号：US09752061

    申请日：2000-12-29

    Applicant: International Business Machines Corporation

    Inventor： Steven H. Voldman ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge

    IPC: H01L029/00 ,  H01L021/336 ,  H01L021/331 ,  H01L021/76

    CPC classification number: H01L29/66287 ,  H01L21/761 ,  H01L21/8249

    Abstract: The preferred embodiment of the present invention provides a buried layer that improves the latch up immunity of digital devices while providing isolation structures that provide noise isolation for both the digital and analog devices. The buried layer of the preferred embodiment is formed to reside within or below the subcollector region in the transistor. Additionally, in the preferred embodiment the subcollector is isolated from buried layer outside the transistor region by deep isolation trenches formed at the edges of the subcollector. Additionally, an array of deep isolation trenches provides increased isolation between devices where needed. Thus, the preferred embodiment of the present invention provides an integrated circuit structure and method that provides improved latchup immunity while also providing improved noise tolerance.

    Abstract translation: 本发明的优选实施例提供了一种掩埋层，其提供数字器件的锁定抗扰性，同时提供为数字和模拟设备提供噪声隔离的隔离结构。 优选实施例的掩埋层形成为位于晶体管内的子集电极区域内或下方。 此外，在优选实施例中，子集电极通过在子集电极的边缘处形成的深隔离沟槽与晶体管区域外的掩埋层隔离。 此外，深度隔离沟槽的阵列提供了在需要的器件之间增加的隔离。 因此，本发明的优选实施例提供了一种集成电路结构和方法，其提供改善的闭锁抑制，同时还提供改善的噪声容限。

    Non-self-aligned SiGe heterojunction bipolar transistor
    2.
    发明申请
    Non-self-aligned SiGe heterojunction bipolar transistor 审中-公开
    非自对准SiGe异质结双极晶体管

    公开(公告)号：US20020197807A1

    公开(公告)日：2002-12-26

    申请号：US09885792

    申请日：2001-06-20

    Applicant: International Business Machines Corporation

    Inventor： Basanth Jagannathan ,  Shwu-Jen Jeng ,  Jeffrey B. Johnson ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Kenneth J. Stein ,  Seshadri Subbanna

    IPC: H01L021/331 ,  H01L021/8222

    CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/7378

    Abstract: A method for making a non-self-aligned, heterojunction bipolar transistor includes forming extrinsic base regions with a PFET source/drain implant aligned with the polysilicon in an emitter stack but which are not directly aligned with an emitter opening defined in that stack. This is achieved by making the emitter pedestal wider than the emitter opening. This advantageously removes the dependency of alignment between the extrinsic base regions and the emitter opening, thereby resulting in fewer process steps, reduced thermal cycles, and improved speed.

    Abstract translation: 用于制造非自对准异质结双极晶体管的方法包括：在发射极堆叠中与多晶硅对准的PFET源极/漏极注入形成非本征基极区域，但不直接对准在该叠层中限定的发射极开口。 这通过使发射器基座宽于发射器开口来实现。 这有利地消除了非本征基区和发射极开口之间的对准的依赖性，从而导致更少的工艺步骤，减少的热循环和改进的速度。

    Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures
    4.
    发明申请
    Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures 有权
    具有原位掺杂，升高的源极和漏极结构的MOSFET器件的制造方法

    公开(公告)号：US20040097047A1

    公开(公告)日：2004-05-20

    申请号：US10300239

    申请日：2002-11-20

    Applicant: International Business Machines Corporation

    Inventor： Wesley C. Natzle ,  Marc W. Cantell ,  Louis D. Lanzerotti ,  Effendi Leobandung ,  Brian L. Tessier ,  Ryan W. Wuthrich

    IPC: H01L021/336

    CPC classification number: H01L21/31116 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/28525 ,  H01L21/28562 ,  H01L29/66628

    Abstract: A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.

    Abstract translation: 一种用于制造FET器件的工艺。 半导体衬底被栅极电介质层覆盖，并且在栅极电介质上形成导电栅电极。 可以加入氧化硅的毯层。 可以在栅电极周围的氧化硅层上形成可选的氮化硅环。 执行两个预清洗步骤。 然后沉积化学氧化物去除气体，用吸附的反应物膜覆盖该装置。 由于吸附的反应物膜与栅极电介质层反应，在栅电极的底部形成氧化硅的圆角，所以除去栅极电介质（除了栅电极之外）。 一个或两个原位掺杂的硅层沉积在源极/漏极区上，以在衬底上方突出超过栅极电介质的表面形成单个或层叠的外延凸起的源/漏区。

    Diffused extrinsic base and method for fabrication
    5.
    发明申请
    Diffused extrinsic base and method for fabrication 失效
    扩散的外在基础和制造方法

    公开(公告)号：US20040014271A1

    公开(公告)日：2004-01-22

    申请号：US10064476

    申请日：2002-07-18

    Applicant: International Business Machines Corporation

    Inventor： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

    IPC: H01L021/8238 ,  H01L027/082 ,  H01L027/102 ,  H01L029/70 ,  H01L031/11

    CPC classification number: H01L29/66287 ,  H01L21/8249 ,  H01L29/1004

    Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device. Additionally, the extrinsic base can be formed with a self-aligned manufacturing process that reduces fabrication complexity.

    Abstract translation: 本发明提供了在集成双极性电路器件中提供增加的晶体管性能的独特的器件结构和方法。 本发明的优选实施例通过提供降低的基极电阻来提供改进的高速性能。 优选的设计通过将掺杂剂从掺杂剂源层扩散到外部碱性区域中形成外部碱基。 掺杂剂的这种扩散形成至少一部分外在碱。 特别地，通过扩散形成与本征基区相邻的部分。 该解决方案避免了植入外在基础的传统解决方案所引起的问题。 具体地说，通过扩散形成外部基体的至少一部分，能够使基部区域的损伤问题最小化。 这种降低的损伤增强了掺杂剂扩散到本征基质中。 另外，形成的外部基极可以具有改善的电阻，导致双极器件的最大频率改善。 另外，外部基座可以通过降低制造复杂性的自对准制造工艺来形成。

    Semiconductor device and method having multiple subcollectors formed on a common wafer
    6.
    发明申请
    Semiconductor device and method having multiple subcollectors formed on a common wafer 失效
    具有形成在公共晶片上的多个子集电极的半导体器件和方法

    公开(公告)号：US20030094673A1

    公开(公告)日：2003-05-22

    申请号：US09991142

    申请日：2001-11-16

    Applicant: International Business Machines Corporation

    Inventor： James S. Dunn ,  Louis D. Lanzerotti ,  Steven H. Voldman

    IPC: H01L027/082

    CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0821

    Abstract: A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.

    Abstract translation: 提供半导体器件和制造具有形成在公共晶片中的多个子集电极的半导体器件的方法，以提供具有不同特性和频率响应的多个结构。 子集电极可以使用不同的剂量或不同的材料种植体来提供，导致在共同晶片上具有不同最佳单位电流增益截止频率（fT）和击穿电压（BVCEO和BVCBO）的器件。

    STRAINED FIN FETS STRUCTURE AND METHOD
    8.
    发明申请
    STRAINED FIN FETS STRUCTURE AND METHOD 有权
    应变鳍结构和方法

    公开(公告)号：US20030178677A1

    公开(公告)日：2003-09-25

    申请号：US10101807

    申请日：2002-03-19

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： William F. Clark ,  David M. Fried ,  Louis D. Lanzerotti ,  Edward J. Nowak

    IPC: H01L021/00 ,  H01L027/01

    CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

    Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

    Abstract translation: 一种在绝缘体上包括绝缘体和硅结构的晶体管的方法和结构。 硅结构包括中心部分和从中心部分的端部延伸的翅片。 第一栅极位于硅结构的中心部分的第一侧上。 应变产生层可以位于硅结构的中心部分的第一栅极和第一侧之间，第二栅极位于硅结构的中心部分的第二侧上。

    Process for implanting a deep subcollector with self-aligned photo registration marks
    10.
    发明申请
    Process for implanting a deep subcollector with self-aligned photo registration marks 失效
    用于植入具有自对准照片对准标记的深子集电极的工艺

    公开(公告)号：US20020146889A1

    公开(公告)日：2002-10-10

    申请号：US09826054

    申请日：2001-04-04

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Douglas D. Coolbaugh ,  Louis D. Lanzerotti ,  John C. Malinowski

    IPC: H01L021/76 ,  H01L021/425

    CPC classification number: G03F9/708 ,  G03F9/7084 ,  H01L21/8249 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a BiCMOS device having a deep subcollector region and self-aligned alignment marks is provided. The inventive method includes the steps of: (a) lithographically forming a first patterned layer comprising a thick dielectric material on a surface of a material stack formed on a semiconductor substrate, the first patterned layer including at least one opening therein and the semiconductor substrate having at least an alignment area; (b) performing a high-energy/high-dose implant through the at least one opening and the material stack so as to form at least one deep subcollector region in the semiconductor substrate; (c) lithographically forming a second patterned layer (photoresist or dielectric) predominately outside the first patterned layer in the alignment area; and (d) etching through the material stack to form alignment marks in the underlying semiconductor substrate using the first patterned layer as an alignment mark mask.

    Abstract translation: 提供了一种形成具有深子集电极区域和自对准对准标记的BiCMOS器件的方法。 本发明的方法包括以下步骤：（a）在形成在半导体衬底上的材料堆叠的表面上光刻地形成包括厚电介质材料的第一图案层，所述第一图案化层包括至少一个开口，并且所述半导体衬底具有 至少一个对准区域; （b）通过所述至少一个开口和所述材料堆叠执行高能/高剂量注入，以便在所述半导体衬底中形成至少一个深子集电极区域; （c）在对准区域中主要在第一图案化层的外部光刻形成第二图案化层（光致抗蚀剂或电介质）; 和（d）使用第一图案化层作为对准标记掩模，蚀刻通过材料堆叠以在下面的半导体衬底中形成对准标记。

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