公开(公告)号：US20030116850A1

公开(公告)日：2003-06-26

申请号：US10026146

申请日：2001-12-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Richard P. Volant ,  Seshadri Subbanna ,  Robert A. Groves ,  John C. Malinowski ,  Kenneth J. Stein ,  Kevin S. Petrarca

IPC分类号： H01L023/48

CPC分类号： H01L23/66 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A passive electrical device includes a first electrical conductor, a second electrical conductor disposed over the first conductor; and a third electrical conductor connecting the first conductor to the second conductor. The said first, second and third conductors are disposed on a semiconductor substrate. The sheet resistivity of the first conductor is approximately equal to the sheet resistivity of the second conductor.

摘要翻译： 无源电气装置包括第一电导体，布置在第一导体上的第二电导体; 以及将第一导体连接到第二导体的第三电导体。 所述第一，第二和第三导体设置在半导体衬底上。 第一导体的薄层电阻率近似等于第二导体的薄层电阻率。

公开(公告)号：US20020163062A1

公开(公告)日：2002-11-07

申请号：US09793643

申请日：2001-02-26

申请人： International Business Machines Corporation

发明人： Ping-Chuan Wang ,  Robert Daniel Edwards ,  John C. Malinowski ,  Vidhya Ramachandran ,  Steffen Kaldor

IPC分类号： H01L023/58 ,  H01L021/302 ,  H01L029/40 ,  H01L021/31 ,  H01L021/461 ,  H01L023/48

CPC分类号： H01L21/02134 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/3144 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/3192 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： A structure/method for reducing the stress between a dielectric, passivation layer and a metallic structure comprising coating the metallic structure with a low stress modulus buffer material, and forming the dielectric passivation layer covering the low stress modulus buffer material. The low stress modulus buffer material is composed of a layer of a polymeric material selected from at least one of the group consisting of a hydrogen/alkane SQ (SilsesQuioxane) resin, polyimide, and a polymer resin. The dielectric, passivation layer is composed of at least one layer of a material selected from at least one of the group consisting of silicon oxide and silicon nitride. A protective layer is formed over the dielectric, passivation layer. The low stress modulus buffer material has a thermal coefficient of expansion between that of the metallic structure and that of the dielectric passivation layer. In particular, the dielectric passivation layer between the metallic structure and the low stress modulus buffer material has a thermal coefficient of expansion between about 5 ppm/null C. and about 20 ppm/null C.

摘要翻译： 一种用于减小电介质，钝化层和金属结构之间的应力的结构/方法，包括用低应力模量缓冲材料涂覆金属结构，以及形成覆盖低应力模量缓冲材料的电介质钝化层。 低应力模量缓冲材料由选自氢/烷烃SQ（SilsesQuioxane）树脂，聚酰亚胺和聚合物树脂中的至少一种的聚合材料层组成。 电介质钝化层由至少一层选自氧化硅和氮化硅中的至少一种的材料组成。 在电介质钝化层上形成保护层。 低应力模量缓冲材料具有在金属结构和介电钝化层的热膨胀系数之间的热膨胀系数。 特别地，金属结构和低应力模量缓冲材料之间的介电钝化层的热膨胀系数在约5ppm /℃至约20ppm /℃之间。

公开(公告)号：US20020146889A1

公开(公告)日：2002-10-10

申请号：US09826054

申请日：2001-04-04

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Douglas D. Coolbaugh ,  Louis D. Lanzerotti ,  John C. Malinowski

IPC分类号： H01L021/76 ,  H01L021/425

CPC分类号： G03F9/708 ,  G03F9/7084 ,  H01L21/8249 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a BiCMOS device having a deep subcollector region and self-aligned alignment marks is provided. The inventive method includes the steps of: (a) lithographically forming a first patterned layer comprising a thick dielectric material on a surface of a material stack formed on a semiconductor substrate, the first patterned layer including at least one opening therein and the semiconductor substrate having at least an alignment area; (b) performing a high-energy/high-dose implant through the at least one opening and the material stack so as to form at least one deep subcollector region in the semiconductor substrate; (c) lithographically forming a second patterned layer (photoresist or dielectric) predominately outside the first patterned layer in the alignment area; and (d) etching through the material stack to form alignment marks in the underlying semiconductor substrate using the first patterned layer as an alignment mark mask.

摘要翻译： 提供了一种形成具有深子集电极区域和自对准对准标记的BiCMOS器件的方法。 本发明的方法包括以下步骤：（a）在形成在半导体衬底上的材料堆叠的表面上光刻地形成包括厚电介质材料的第一图案层，所述第一图案化层包括至少一个开口，并且所述半导体衬底具有 至少一个对准区域; （b）通过所述至少一个开口和所述材料堆叠执行高能/高剂量注入，以便在所述半导体衬底中形成至少一个深子集电极区域; （c）在对准区域中主要在第一图案化层的外部光刻形成第二图案化层（光致抗蚀剂或电介质）; 和（d）使用第一图案化层作为对准标记掩模，蚀刻通过材料堆叠以在下面的半导体衬底中形成对准标记。