公开(公告)号：US10546992B2

公开(公告)日：2020-01-28

申请号：US16021202

申请日：2018-06-28

Applicant: International Business Machines Corporation

Inventor： Andreas Fuhrer ,  Andreas Kuhlmann ,  Ute Drechsler ,  Veeresh V. Deshpande ,  Stefan Filipp ,  Marc Ganzhorn

IPC: H01L39/02 ,  H01P3/08 ,  H01L39/24 ,  H01L39/22 ,  G06N10/00

Abstract: Embodiments are directed to a superconducting microwave circuit. The circuit includes a substrate and two electrodes. The latter form an electrode pair dimensioned so as to support an electromagnetic field, which allows the circuit to be operated in the microwave domain. The substrate exhibits a raised portion, which includes a top surface and two lateral surfaces. The top surface connects the two lateral surfaces, which show respective undercuts (on the lateral sides of the raised portions). Each of the electrodes includes a structure that includes a potentially superconducting material. Two protruding structures are accordingly formed, which are shaped complementarily to the respective undercuts. This way, the shaped structure of each of the electrodes protrudes toward the other one of the electrodes of the pair.

公开(公告)号：US10395168B2

公开(公告)日：2019-08-27

申请号：US14922300

申请日：2015-10-26

Applicant: International Business Machines Corporation

Inventor： Stefan Abel ,  Lukas Czomomaz ,  Veeresh V. Deshpande ,  Jean Fompeyrine

IPC: G06N3/067 ,  G06N3/04

Abstract: A reservoir computing neuromorphic network includes an input layer comprising one or more input nodes, a reservoir layer comprising a plurality of reservoir nodes, and an output layer comprising one or more output nodes. A portion of at least one of the input layer, the reservoir layer, and the output layer includes an optically tunable material.

公开(公告)号：US10254642B2

公开(公告)日：2019-04-09

申请号：US15884573

申请日：2018-01-31

Applicant: International Business Machines Corporation

Inventor： Veeresh V. Deshpande ,  Howard S. Landis ,  Arun Sankar Mampazhy ,  Neelima Mandloi

IPC: G03F1/36 ,  G03F7/20 ,  G06F17/50

Abstract: Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.

公开(公告)号：US10103234B1

公开(公告)日：2018-10-16

申请号：US15800499

申请日：2017-11-01

Applicant: International Business Machines Corporation

Inventor： Lukas Czornomaz ,  Veeresh V. Deshpande ,  Vladimir Djara

IPC: H01L21/336 ,  H01L29/417 ,  H01L21/321 ,  H01L29/66 ,  H01L29/20 ,  H01L29/161 ,  H01L29/06 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L21/3105 ,  H01L29/08 ,  H01L21/285

Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.

公开(公告)号：US20180294338A1

公开(公告)日：2018-10-11

申请号：US15800499

申请日：2017-11-01

Applicant: International Business Machines Corporation

Inventor： Lukas Czornomaz ,  Veeresh V. Deshpande ,  Vladimir Djara

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/161 ,  H01L29/08 ,  H01L29/06 ,  H01L21/768 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/285

Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.

公开(公告)号：US09917164B1

公开(公告)日：2018-03-13

申请号：US15481537

申请日：2017-04-07

Applicant: International Business Machines Corporation

Inventor： Lukas Czornomaz ,  Veeresh V. Deshpande ,  Vladimir Djara

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L21/321 ,  H01L21/285

CPC classification number: H01L29/41783 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66522 ,  H01L29/6656

Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.

公开(公告)号：US11157807B2

公开(公告)日：2021-10-26

申请号：US15953438

申请日：2018-04-14

Applicant: International Business Machines Corporation

Inventor： Stefan Abel ,  Veeresh V. Deshpande ,  Jean Fompeyrine

IPC: G06N3/067 ,  H04B10/40 ,  H04L5/00 ,  G02F1/355 ,  G02F1/35 ,  G06N3/04 ,  G06N3/08

Abstract: An integrated optical circuit for an optical neural network is provided. The optical circuit is configured to process a plurality of phase-encoded optical input signals and to provide a phase-encoded optical output signal depending on the phase-encoded optical input signals. The phase-encoded optical output signal emulates a neuron functionality with respect to the plurality of phase-encoded optical input signals. Such an embodied optical circuit uses the phase to encode information in the optical domain. A related method and a related design structure are further provided.

公开(公告)号：US10304934B2

公开(公告)日：2019-05-28

申请号：US16100353

申请日：2018-08-10

Applicant: International Business Machines Corporation

Inventor： Lukas Czornomaz ,  Veeresh V. Deshpande ,  Vladimir Djara

IPC: H01L21/3105 ,  H01L21/768 ,  H01L29/786 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L21/285

Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.

公开(公告)号：US20180350925A1

公开(公告)日：2018-12-06

申请号：US16100353

申请日：2018-08-10

Applicant: International Business Machines Corporation

Inventor： Lukas Czornomaz ,  Veeresh V. Deshpande ,  Vladimir Djara

IPC: H01L29/417

CPC classification number: H01L29/41783 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66522 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/786

Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.

公开(公告)号：US09984929B1

公开(公告)日：2018-05-29

申请号：US15800243

申请日：2017-11-01

Applicant: International Business Machines Corporation

Inventor： Lukas Czornomaz ,  Veeresh V. Deshpande ,  Vladimir Djara ,  Pouya Hashemi

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/306 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/417

CPC classification number: H01L21/823418 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/84 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66553

Abstract: The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.