ACTUATOR LAYER PATTERNING WITH TOPOGRAPHY
    1.
    发明公开

    公开(公告)号:US20230202835A1

    公开(公告)日:2023-06-29

    申请号:US18115178

    申请日:2023-02-28

    申请人: InvenSense, Inc.

    IPC分类号: B81C1/00 B81B7/00

    摘要: A method including fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a hardmask on a second side of the device wafer, wherein the second side is planar. An etch stop layer is deposited over the hardmask and an exposed portion of the second side of the device wafer. A dielectric layer is formed over the etch stop layer. A via is formed within the dielectric layer. The via is filled with conductive material. A eutectic bond layer is formed over the conductive material. Portions of the dielectric layer uncovered by the eutectic bond layer is etched to expose the etch stop layer. The exposed portions of the etch stop layer is etched. A micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.

    SENSOR WITH DIMPLE FEATURES AND IMPROVED OUT-OF-PLANE STICTION

    公开(公告)号:US20230100960A1

    公开(公告)日:2023-03-30

    申请号:US18071322

    申请日:2022-11-29

    申请人: InvenSense, Inc.

    IPC分类号: B81C1/00 B81B7/00

    摘要: A method includes fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a first mask on a second side of the device wafer, wherein the second side is planar. A plurality of dimple features is formed on an exposed portion on the second side of the device wafer. The first mask is removed from the second side of the device wafer. A second mask is deposited on the second side of the device wafer that corresponds to a standoff. An exposed portion on the second side of the device wafer is etched to form the standoff. The second mask is removed. A rough polysilicon layer is deposited on the second side of the device wafer. A eutectic bond layer is deposited on the standoff. In some embodiments, a micro-electromechanical system (MEMS) device pattern is etched into the device wafer.

    Sensor with dimple features and improved out-of-plane stiction

    公开(公告)号:US11919769B2

    公开(公告)日:2024-03-05

    申请号:US18071322

    申请日:2022-11-29

    申请人: InvenSense, Inc.

    IPC分类号: B81C1/00 B81B7/00

    摘要: A method includes fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a first mask on a second side of the device wafer, wherein the second side is planar. A plurality of dimple features is formed on an exposed portion on the second side of the device wafer. The first mask is removed from the second side of the device wafer. A second mask is deposited on the second side of the device wafer that corresponds to a standoff. An exposed portion on the second side of the device wafer is etched to form the standoff. The second mask is removed. A rough polysilicon layer is deposited on the second side of the device wafer. A eutectic bond layer is deposited on the standoff. In some embodiments, a micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.

    Stiction reduction system and method thereof

    公开(公告)号:US11661332B2

    公开(公告)日:2023-05-30

    申请号:US16795514

    申请日:2020-02-19

    申请人: InvenSense, Inc.

    IPC分类号: H01L21/311 B81B3/00 B81C1/00

    摘要: Methods and systems for reducing stiction through roughening the surface and reducing the contact area in MEMS devices are disclosed. A method includes fabricating bumpstops on a surface of a MEMS device substrate to reduce stiction. Another method is directed to applying roughening etchant to a surface of a silicon substrate to enhance roughness after cavity etch and before removal of hardmask. Another embodiment described herein is directed to a method to reduce contact area between proof mass and UCAV (“upper cavity”) substrate surface with minimal impact on the cavity volume by introducing a shallow etch process step and maintaining high pressure in accelerometer cavity. Another method is described as to increasing the surface roughness of a UCAV substrate surface by depositing a rough layer (e.g. polysilicon) on the surface of the substrate and etching back the rough layer to transfer the roughness.

    SELECTIVE SELF-ASSEMBLED MONOLAYER PATTERNING WITH SACRIFICIAL LAYER FOR DEVICES

    公开(公告)号:US20210107785A1

    公开(公告)日:2021-04-15

    申请号:US17028552

    申请日:2020-09-22

    申请人: INVENSENSE, INC.

    摘要: Selective self-assembled monolayer patterning with sacrificial layer for devices is provided herein. A sensor device can include a handle layer and a device layer that comprises a first side and a second side. First portions of the first side are operatively connected to defined portions of the handle layer. At least one area of the second side comprises an anti-stiction area formed with an anti-stiction coating. The device can also include a Complementary Metal-Oxide-Semiconductor (CMOS) wafer operatively connected to second portions of the second side of the device layer. The CMOS wafer comprises at least one bump stop. The anti-stiction area faces the at least one bump stop.

    Actuator layer patterning with topography

    公开(公告)号:US10745270B2

    公开(公告)日:2020-08-18

    申请号:US16440860

    申请日:2019-06-13

    申请人: InvenSense, Inc.

    IPC分类号: B81B7/02 B81C1/00 B81C3/00

    摘要: Provided herein is a method including fusion bonding a handle wafer to a first side of a device wafer. A hardmask is deposited on a second side of the device wafer, wherein the second side is planar. The hardmask is etched to form a MEMS device pattern and a standoff pattern. Standoffs are formed on the device wafer, wherein the standoffs are defined by the standoff pattern. A eutectic bond metal is deposited on the standoffs, the device wafer, and the hardmask. A first photoresist is deposited and removed, such that the first photoresist covers the standoffs. The eutectic bond metal is etched using the first photoresist. The MEMS device pattern is etched into the device wafer. The first photoresist and the hardmask are removed.

    MEMS tab removal process
    7.
    发明授权

    公开(公告)号:US11905170B2

    公开(公告)日:2024-02-20

    申请号:US17547388

    申请日:2021-12-10

    申请人: InvenSense, Inc.

    IPC分类号: B81C1/00

    CPC分类号: B81C1/00896 B81C2203/0785

    摘要: A method includes tab dicing a region of a tab region disposed between a first die and a second die. The tab region structurally connects the first die to the second die each including a MEMS device eutecticly bonded to a CMOS device. The tab region includes a handle wafer layer disposed over a fusion bond oxide layer that is disposed on an ACT layer. The tab region is positioned above a CMOS tab region that with the first and second die form a cavity therein. The tab dicing cuts through the handle wafer layer and leaves a portion of the fusion bond oxide layer underneath the handle wafer layer to form an oxide tether within the tab region. The oxide tether maintains the tab region in place and above the CMOS tab region. Subsequent to the tab dicing the first region, the tab region is removed.

    Actuator layer patterning with topography

    公开(公告)号:US11618674B2

    公开(公告)日:2023-04-04

    申请号:US17195346

    申请日:2021-03-08

    申请人: InvenSense, Inc.

    IPC分类号: B81C1/00 B81B7/00

    摘要: A method including fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a hardmask on a second side of the device wafer, wherein the second side is planar. An etch stop layer is deposited over the hardmask and an exposed portion of the second side of the device wafer. A dielectric layer is formed over the etch stop layer. A via is formed within the dielectric layer. The via is filled with conductive material. A eutectic bond layer is formed over the conductive material. Portions of the dielectric layer uncovered by the eutectic bond layer is etched to expose the etch stop layer. The exposed portions of the etch stop layer is etched. A micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.

    METHOD AND SYSTEM FOR FABRICATING A MEMS DEVICE

    公开(公告)号:US20230045257A1

    公开(公告)日:2023-02-09

    申请号:US17877151

    申请日:2022-07-29

    申请人: InvenSense, Inc.

    IPC分类号: B81C1/00

    摘要: A device includes a substrate and an intermetal dielectric (IMD) layer disposed over the substrate. The device also includes a first plurality of polysilicon layers disposed over the IMD layer and over a bumpstop. The device also includes a second plurality of polysilicon layers disposed within the IMD layer. The device includes a patterned actuator layer with a first side and a second side, wherein the first side of the patterned actuator layer is lined with a polysilicon layer, and wherein the first side of the patterned actuator layer faces the bumpstop. The device further includes a standoff formed over the IMD layer, a via through the standoff making electrical contact with the polysilicon layer of the actuator and a portion of the second plurality of polysilicon layers and a bond material disposed on the second side of the patterned actuator layer.