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    LOW POWER DELAY CONTROLLED ZERO SENSITIVE SENSE AMPLIFIER
    1.
    发明申请
    LOW POWER DELAY CONTROLLED ZERO SENSITIVE SENSE AMPLIFIER 有权
    低功率延迟控制的零感应感测放大器

    公开(公告)号：US20060209606A1

    公开(公告)日：2006-09-21

    申请号：US11081276

    申请日：2005-03-16

    申请人： Iqbal Rajwani ,  Satish Damaraju

    发明人： Iqbal Rajwani ,  Satish Damaraju

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12 ,  G11C7/062 ,  G11C7/067

    摘要： In one embodiment of the invention an integrated circuit is provided including a sense amplifier to read data from a memory cell that has a first transfer gate, a second transfer gate, a comparator, and a control circuit. The first transfer gate has a first pole coupled to a positive power supply. The second transfer gate has a first pole coupled to a bitline of the memory cell. The comparator has a first input coupled to a second pole of the first transfer gate, a second input coupled to a second pole of the second transfer gate, and an output coupled to the second input. The comparator compares signals on the first and second inputs and selectively generates a greater differential signal there-between. The control circuit turns off the comparator responsive to a logical zero being read from the memory cell avoiding the generation of the greater differential signal.

    摘要翻译： 在本发明的一个实施例中，提供一种集成电路，其包括用于从具有第一传输门，第二传输门，比较器和控制电路的存储单元读取数据的读出放大器。 第一传输门具有耦合到正电源的第一极。 第二传输门具有耦合到存储单元的位线的第一极。 比较器具有耦合到第一传输门的第二极的第一输入，耦合到第二传输门的第二极的第二输入和耦合到第二输入的输出。 比较器比较第一和第二输入端的信号，并选择性地在其间产生较大的差分信号。 控制电路响应于从存储器单元读取的逻辑零而关闭比较器，从而避免产生更大的差分信号。

    Low power delay controlled zero sensitive sense amplifier
    2.
    发明授权
    Low power delay controlled zero sensitive sense amplifier 有权
    低功耗延迟控制零敏感读出放大器

    公开(公告)号：US07130236B2

    公开(公告)日：2006-10-31

    申请号：US11081276

    申请日：2005-03-16

    申请人： Iqbal Rajwani ,  Satish Damaraju

    发明人： Iqbal Rajwani ,  Satish Damaraju

    IPC分类号： G11C7/02

    CPC分类号： G11C7/12 ,  G11C7/062 ,  G11C7/067

    摘要： In one embodiment of the invention an integrated circuit is provided including a sense amplifier to read data from a memory cell that has a first transfer gate, a second transfer gate, a comparator, and a control circuit. The first transfer gate has a first pole coupled to a positive power supply. The second transfer gate has a first pole coupled to a bitline of the memory cell. The comparator has a first input coupled to a second pole of the first transfer gate, a second input coupled to a second pole of the second transfer gate, and an output coupled to the second input. The comparator compares signals on the first and second inputs and selectively generates a greater differential signal there-between. The control circuit turns off the comparator responsive to a logical zero being read from the memory cell avoiding the generation of the greater differential signal.

    摘要翻译： 在本发明的一个实施例中，提供一种集成电路，其包括用于从具有第一传输门，第二传输门，比较器和控制电路的存储单元读取数据的读出放大器。 第一传输门具有耦合到正电源的第一极。 第二传输门具有耦合到存储单元的位线的第一极。 比较器具有耦合到第一传输门的第二极的第一输入，耦合到第二传输门的第二极的第二输入和耦合到第二输入的输出。 比较器比较第一和第二输入端的信号，并选择性地在其间产生较大的差分信号。 控制电路响应于从存储器单元读取的逻辑零而关闭比较器，从而避免产生更大的差分信号。

    Reducing power consumption in a sequential cache
    4.
    发明申请
    Reducing power consumption in a sequential cache 有权
    降低顺序缓存中的功耗

    公开(公告)号：US20060143382A1

    公开(公告)日：2006-06-29

    申请号：US11027413

    申请日：2004-12-29

    申请人： Satish Damaraju ,  Subramaniam Maiyuran ,  Peter Smith ,  Navin Monteiro

    发明人： Satish Damaraju ,  Subramaniam Maiyuran ,  Peter Smith ,  Navin Monteiro

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0875 ,  G06F9/3802 ,  G06F9/3804 ,  G06F12/0846 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

    摘要： In one embodiment, the present invention includes a cache memory, which may be a sequential cache, having multiple banks. Each of the banks includes a data array, a decoder coupled to the data array to select a set of the data array, and a sense amplifier. Only a bank to be accessed may be powered, and in some embodiments early way information may be used to maintain remaining banks in a power reduced state. In some embodiments, clock gating may be used to maintain various components of the cache memory in a power reduced state. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括高速缓冲存储器，其可以是具有多个存储体的顺序高速缓存。 每个存储体包括数据阵列，耦合到数据阵列的解码器以选择一组数据阵列，以及读出放大器。 只有要访问的存储体可以被供电，并且在一些实施例中，可以使用早期路径信息来维持处于功率降低状态的剩余存储体。 在一些实施例中，可以使用时钟选通来维持处于功率降低状态的高速缓冲存储器的各种组件。 描述和要求保护其他实施例。

    Low power cache architecture
    6.
    发明授权
    Low power cache architecture 有权

    公开(公告)号：US07136984B2

    公开(公告)日：2006-11-14

    申请号：US11000054

    申请日：2004-12-01

    申请人： Subramaniam J. Maiyuran ,  Lyman Moulton ,  Salvador Palanca ,  Satish Damaraju

    发明人： Subramaniam J. Maiyuran ,  Lyman Moulton ,  Salvador Palanca ,  Satish Damaraju

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0864 ,  G06F12/0846 ,  G06F2212/1028 ,  Y02D10/13

    摘要： In a processor cache, cache circuits are mapped into one or more logical modules. Each module may be powered down independently of other modules in response to microinstructions processed by the cache. Power control may be applied on a microinstruction-by-microinstruction basis. Because the microinstructions determine which modules are used, power savings may be achieved by powering down those modules that are not used. A cache layout organization may be modified to distribute a limited number of ways across addressable cache banks. By associating fewer than a total number of ways to a bank (for example, one or two ways), the size of memory clusters within the bank may be reduced. The reduction in this size of the memory cluster contributes reduces the power needed for an address decoder to address sets within the bank.

    System and method for reducing power consumption in a device using register files
    7.
    发明授权
    System and method for reducing power consumption in a device using register files 有权
    使用寄存器文件降低设备功耗的系统和方法

    公开(公告)号：US08356202B2

    公开(公告)日：2013-01-15

    申请号：US12057685

    申请日：2008-03-28

    申请人： Satish Damaraju ,  Scott Siers ,  Omar Malik

    发明人： Satish Damaraju ,  Scott Siers ,  Omar Malik

    IPC分类号： G06F1/04 ,  G06F1/26 ,  G11C7/10

    CPC分类号： G06F9/30141

    摘要： A device and method for reducing the power consumption of an electronic device using register file with bypass mechanism. The width of a pulse controlling the word write operation may be extended twice as long so that the extended portion substantially overlaps a following word read pulse. The extension of the pulse width of the read operation may enable lowering the Vcc Min value for the electronic device and thus may lower the power consumption of the device.

    摘要翻译： 一种使用具有旁路机构的寄存器文件降低电子装置的功耗的装置和方法。 控制字写入操作的脉冲的宽度可以延长两倍，使得延伸部分基本上与接续字读取脉冲重叠。 读取操作的脉冲宽度的扩展可以使电子设备的Vcc最小值降低，从而可能降低设备的功耗。

    SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A DEVICE USING REGISTER FILES
    9.
    发明申请
    SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A DEVICE USING REGISTER FILES 有权
    使用寄存器文件在设备中降低功耗的系统和方法

    公开(公告)号：US20090249041A1

    公开(公告)日：2009-10-01

    申请号：US12057685

    申请日：2008-03-28

    申请人： Satish Damaraju ,  Scott Siers ,  Omar Malik

    发明人： Satish Damaraju ,  Scott Siers ,  Omar Malik

    IPC分类号： G06F1/04 ,  G06F9/305

    CPC分类号： G06F9/30141

    摘要： A device and method for reducing the power consumption of an electronic device using register file with bypass mechanism. The width of a pulse controlling the word write operation may be extended twice as long so that the extended portion substantially overlaps a following word read pulse. The extension of the pulse width of the read operation may enable lowering the Vcc Min value for the electronic device and thus may lower the power consumption of the device.

    摘要翻译： 一种使用具有旁路机构的寄存器文件降低电子装置的功耗的装置和方法。 控制字写入操作的脉冲的宽度可以延长两倍，使得延伸部分基本上与接续字读取脉冲重叠。 读取操作的脉冲宽度的扩展可以使电子设备的Vcc最小值降低，从而可能降低设备的功耗。

    Low power cache architecture
    10.
    发明申请
    Low power cache architecture 有权
    低功耗缓存架构

    公开(公告)号：US20050097277A1

    公开(公告)日：2005-05-05

    申请号：US11000054

    申请日：2004-12-01

    申请人： Subramaniam Maiyuran ,  Lyman Moulton ,  Salvador Palanca ,  Satish Damaraju

    发明人： Subramaniam Maiyuran ,  Lyman Moulton ,  Salvador Palanca ,  Satish Damaraju

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0864 ,  G06F12/0846 ,  G06F2212/1028 ,  Y02D10/13

    摘要： In a processor cache, cache circuits are mapped into one or more logical modules. Each module may be powered down independently of other modules in response to microinstructions processed by the cache. Power control may be applied on a microinstruction-by-microinstruction basis. Because the microinstructions determine which modules are used, power savings may be achieved by powering down those modules that are not used. A cache layout organization may be modified to distribute a limited number of ways across addressable cache banks. By associating fewer than a total number of ways to a bank (for example, one or two ways), the size of memory clusters within the bank may be reduced. The reduction in this size of the memory cluster contributes reduces the power needed for an address decoder to address sets within the bank.

    摘要翻译： 在处理器高速缓存中，高速缓存电路被映射到一个或多个逻辑模块中。 响应于由高速缓存处理的微指令，每个模块可以独立于其它模块被关闭。 功率控制可以在微指令的基础上应用。 因为微指令决定了哪些模块被使用，所以可以通过关闭那些未使用的模块来实现功率节省。 可以修改高速缓存布局组织以在可寻址缓存组中分布有限数量的方式。 通过将小于总数量的方式与银行相关联（例如，一种或两种方式），可以减少银行内的存储器簇的大小。 存储器簇的这种尺寸的减小有助于减少地址解码器对存储体内的集合进行寻址所需的功率。