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公开(公告)号：US08081502B1
公开(公告)日：2011-12-20
申请号：US12345560
申请日：2008-12-29
申请人： Irfan Rahim , Jun Liu , Andy L. Lee , William Bradley Vest , Lu Zhou , Qi Xiang , Yanzhong Yu , Jeffrey Xiaoqi Tung , Albert Ratnakumar
发明人： Irfan Rahim , Jun Liu , Andy L. Lee , William Bradley Vest , Lu Zhou , Qi Xiang , Yanzhong Yu , Jeffrey Xiaoqi Tung , Albert Ratnakumar
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： An integrated circuit with memory elements is provided. The memory elements may have memory element transistors with body terminals. Body bias control circuitry may supply body bias voltages that strengthen or weaken memory element transistors to improve read and write margins. The body bias control circuitry may dynamically control body bias voltages so that time-varying body bias voltages are supplied to memory element transistors. Address transistors and latch transistors in the memory elements may be selectively strengthened and weakened. Process variations may be compensated by weakening fast transistors and strengthening slow transistors with body bias adjustments.
摘要翻译： 提供了一种具有存储元件的集成电路。 存储器元件可以具有带有主体端子的存储器元件晶体管。 体偏置控制电路可以提供加强或削弱存储元件晶体管的体偏置电压，以改善读和写余量。 体偏置控制电路可以动态地控制体偏置电压，从而将时变体偏置电压提供给存储元件晶体管。 存储元件中的地址晶体管和锁存晶体管可以被选择性地加强和削弱。 过程变化可以通过削弱快速晶体管和加强具有体偏置调整的慢晶体管来补偿。
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公开(公告)号：US08482963B1
公开(公告)日：2013-07-09
申请号：US12629831
申请日：2009-12-02
申请人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
发明人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.
摘要翻译： 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。
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公开(公告)号：US08633731B1
公开(公告)日：2014-01-21
申请号：US13206401
申请日：2011-08-09
申请人： Irfan Rahim , Mao Du , Jeffrey Xiaoqi Tung , Jun Liu , Qi Xiang
发明人： Irfan Rahim , Mao Du , Jeffrey Xiaoqi Tung , Jun Liu , Qi Xiang
IPC分类号： G06F7/38
CPC分类号： H03K19/1733 , G11C8/16 , G11C11/419
摘要： Integrated circuits such as programmable integrated circuits may have configuration random-access memory elements. The configuration random-access memory elements may be loaded with configuration data to customize programmable circuitry on the integrated circuits. Each memory element may have a bistable element that is powered using a positive power supply voltage and a negative power supply voltage. Programmable transistors in the programmable circuitry may have gates coupled to outputs of the bistable elements. The programmable transistors may have gate insulators that are thinner than gate insulators in the transistors of the bistable elements and may have threshold voltages of about zero volts. During operation, some of the configuration random-access memory elements may supply negative voltages to their associated programmable transistors so that the programmable transistors are provided with gate-source voltages of less than zero volts.
摘要翻译： 诸如可编程集成电路的集成电路可以具有配置随机存取存储器元件。 配置随机存取存储器元件可以被加载配置数据以定制集成电路上的可编程电路。 每个存储元件可以具有使用正电源电压和负电源电压供电的双稳态元件。 可编程电路中的可编程晶体管可以具有耦合到双稳态元件的输出的栅极。 可编程晶体管可以具有比双稳态元件的晶体管中的栅极绝缘体更薄的栅极绝缘体，并且可以具有约零伏特的阈值电压。 在操作期间，一些配置随机存取存储器元件可以向其相关联的可编程晶体管提供负电压，使得可编程晶体管具有小于零伏的栅极 - 源极电压。
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公开(公告)号：US08804407B1
公开(公告)日：2014-08-12
申请号：US13181219
申请日：2011-07-12
申请人： Jun Liu , Albert Ratnakumar , Irfan Rahim , Qi Xiang
发明人： Jun Liu , Albert Ratnakumar , Irfan Rahim , Qi Xiang
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H03K2217/0054
摘要： An IC that includes a memory cell and a pass gate coupled to the memory cell, where the pass gate includes a PMOS transistor, is described. In one implementation, the PMOS transistor has a negative threshold voltage. In one implementation, the memory cell includes thick oxide transistors.
摘要翻译： 描述了包括耦合到存储器单元的存储单元和通过栅极的IC，其中栅极包括PMOS晶体管。 在一个实现中，PMOS晶体管具有负阈值电压。 在一个实现中，存储单元包括厚的氧化物晶体管。
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公开(公告)号：US08797790B1
公开(公告)日：2014-08-05
申请号：US12568638
申请日：2009-09-28
IPC分类号： G11C11/00 , G11C11/412 , G11C8/16
CPC分类号： G11C11/412 , G11C5/005 , G11C5/06 , G11C8/16 , G11C11/4125
摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. Each memory element may each have four inverter-like transistor pairs that form a bistable element, a pair of address transistors, and a pair of relatively weak transistors connected between two of the inverters that create a common output node which is resistant to rapid changes to its state. The transistors may be connected in a pattern that forms a bistable memory element that is resistant to soft error upset events due to radiation strikes. Data may be loaded into and read out of the memory element using the address transistor pair.
摘要翻译： 提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。 每个存储元件可以各自具有形成双稳态元件，一对地址晶体管和连接在两个逆变器之间的一对相对较弱的晶体管的四个逆变器状晶体管对，其形成公共输出节点，其抵抗快速变化 它的状态。 晶体管可以以形成双稳态存储器元件的图案连接，该双稳态存储器元件由于辐射打击而抵抗软错误不正常事件。 可以使用地址晶体管对将数据加载到存储器元件中并从存储器元件读出。
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公开(公告)号：US20100321984A1
公开(公告)日：2010-12-23
申请号：US12868575
申请日：2010-08-25
IPC分类号： G11C11/24
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。 配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。 每个存储器元件具有存储该存储器元件的数据的电容器。 一对交叉耦合的反相器连接到电容器。 逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。 每个配置随机存取存储器元件可以具有透明晶体管。 电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。 逆变器可以用升高的电源电压供电。
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公开(公告)号：US08030962B2
公开(公告)日：2011-10-04
申请号：US12868575
申请日：2010-08-25
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。 配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。 每个存储器元件具有存储该存储器元件的数据的电容器。 一对交叉耦合的反相器连接到电容器。 逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。 每个配置随机存取存储器元件可以具有透明晶体管。 电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。 逆变器可以用升高的电源电压供电。
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公开(公告)号：US20080169836A1
公开(公告)日：2008-07-17
申请号：US11653001
申请日：2007-01-12
IPC分类号： H03K19/094 , G11C5/02
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。 配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。 每个存储器元件具有存储该存储器元件的数据的电容器。 一对交叉耦合的反相器连接到电容器。 逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。 每个配置随机存取存储器元件可以具有透明晶体管。 电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。 逆变器可以用升高的电源电压供电。
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公开(公告)号：US08289755B1
公开(公告)日：2012-10-16
申请号：US12571346
申请日：2009-09-30
IPC分类号： G11C11/00
CPC分类号： G11C11/4125
摘要： Memory elements are provided that exhibit immunity to soft error upsets. The memory elements may have cross-coupled inverters. The inverters may be implemented using programmable Schmitt triggers. The memory elements may be locked and unlocked by providing appropriate power supply voltages to the Schmitt trigger. The memory elements may each have four inverter-like transistor pairs that form a bistable element, at least one address transistor, and at least one write enable transistor. The write enable transistor may bridge two of the four nodes. The memory elements may be locked and unlocked by turning the write enable transistor on and off. When a memory element is unlocked, the memory element is less resistant to changes in state, thereby facilitating write operations. When the memory element is locked, the memory element may exhibit enhanced immunity to soft error upsets.
摘要翻译： 提供了显示对软错误扰乱的抗扰度的内存元素。 存储器元件可以具有交叉耦合的反相器。 可以使用可编程施密特触发器来实现逆变器。 存储器元件可以通过向施密特触发器提供适当的电源电压来锁定和解锁。 存储元件可以各自具有形成双稳态元件，至少一个地址晶体管和至少一个写使能晶体管的四个逆变器状晶体管对。 写使能晶体管可以桥接四个节点中的两个。 存储元件可以通过打开和关闭写使能晶体管来锁定和解锁。 当存储器元件被解锁时，存储元件对状态变化的抵抗力较小，从而便于写操作。 当存储器元件被锁定时，存储元件可以表现出对软错误扰动的增强的抗扰性。
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公开(公告)号：US07800400B2
公开(公告)日：2010-09-21
申请号：US11653001
申请日：2007-01-12
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译： 提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。 配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。 每个存储器元件具有存储该存储器元件的数据的电容器。 一对交叉耦合的反相器连接到电容器。 逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。 每个配置随机存取存储器元件可以具有透明晶体管。 电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。 逆变器可以用升高的电源电压供电。
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