公开(公告)号：US08482963B1

公开(公告)日：2013-07-09

申请号：US12629831

申请日：2009-12-02

申请人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

发明人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

摘要翻译： 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。

公开(公告)号：US08804407B1

公开(公告)日：2014-08-12

申请号：US13181219

申请日：2011-07-12

申请人： Jun Liu ,  Albert Ratnakumar ,  Irfan Rahim ,  Qi Xiang

发明人： Jun Liu ,  Albert Ratnakumar ,  Irfan Rahim ,  Qi Xiang

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H03K2217/0054

摘要： An IC that includes a memory cell and a pass gate coupled to the memory cell, where the pass gate includes a PMOS transistor, is described. In one implementation, the PMOS transistor has a negative threshold voltage. In one implementation, the memory cell includes thick oxide transistors.

摘要翻译： 描述了包括耦合到存储器单元的存储单元和通过栅极的IC，其中栅极包括PMOS晶体管。 在一个实现中，PMOS晶体管具有负阈值电压。 在一个实现中，存储单元包括厚的氧化物晶体管。

公开(公告)号：US08081502B1

公开(公告)日：2011-12-20

申请号：US12345560

申请日：2008-12-29

申请人： Irfan Rahim ,  Jun Liu ,  Andy L. Lee ,  William Bradley Vest ,  Lu Zhou ,  Qi Xiang ,  Yanzhong Yu ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar

发明人： Irfan Rahim ,  Jun Liu ,  Andy L. Lee ,  William Bradley Vest ,  Lu Zhou ,  Qi Xiang ,  Yanzhong Yu ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： An integrated circuit with memory elements is provided. The memory elements may have memory element transistors with body terminals. Body bias control circuitry may supply body bias voltages that strengthen or weaken memory element transistors to improve read and write margins. The body bias control circuitry may dynamically control body bias voltages so that time-varying body bias voltages are supplied to memory element transistors. Address transistors and latch transistors in the memory elements may be selectively strengthened and weakened. Process variations may be compensated by weakening fast transistors and strengthening slow transistors with body bias adjustments.

摘要翻译： 提供了一种具有存储元件的集成电路。 存储器元件可以具有带有主体端子的存储器元件晶体管。 体偏置控制电路可以提供加强或削弱存储元件晶体管的体偏置电压，以改善读和写余量。 体偏置控制电路可以动态地控制体偏置电压，从而将时变体偏置电压提供给存储元件晶体管。 存储元件中的地址晶体管和锁存晶体管可以被选择性地加强和削弱。 过程变化可以通过削弱快速晶体管和加强具有体偏置调整的慢晶体管来补偿。

公开(公告)号：US08921170B1

公开(公告)日：2014-12-30

申请号：US13408959

申请日：2012-02-29

申请人： Jun Liu ,  Albert Ratnakumar ,  Mark T. Chan ,  Irfan Rahim

发明人： Jun Liu ,  Albert Ratnakumar ,  Mark T. Chan ,  Irfan Rahim

IPC分类号： H01L21/338

CPC分类号： H01L21/823418 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/082 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66659

摘要： Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors. Asymmetric pass transistors may be controlled by static control signals from memory elements to implement circuits such as programmable multiplexers.

摘要翻译： 不对称晶体管，例如不对称传输晶体管可以形成在集成电路上。 不对称晶体管可以具有栅极结构。 可以在每个晶体管栅极结构的相对侧上的源极漏极中形成对称的袋状植入物。 选择性加热可用于不对称地扩散植入物。 可以通过在半导体衬底上图案化栅极结构来实现选择性加热，使得相邻栅极结构之间的间隔变化。 给定的栅极结构可以位于与给定栅极结构不同的相应距离处间隔开的第一和第二相邻栅极结构之间。 较大的栅极结构间隔导致比较小栅极结构间隔更大的衬底温度升高。 在较大的温度上升的情况下，口袋植入物在衬底的部分扩散，产生不对称晶体管。 不对称传输晶体管可以由来自存储器元件的静态控制信号来控制，以实现诸如可编程多路复用器之类的电路。

公开(公告)号：US08138797B1

公开(公告)日：2012-03-20

申请号：US12790660

申请日：2010-05-28

申请人： Jun Liu ,  Albert Ratnakumar ,  Mark T. Chan ,  Irfan Rahim

发明人： Jun Liu ,  Albert Ratnakumar ,  Mark T. Chan ,  Irfan Rahim

IPC分类号： H01L25/00 ,  H03K19/00

CPC分类号： H01L21/823418 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/082 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66659

摘要： Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors. Asymmetric pass transistors may be controlled by static control signals from memory elements to implement circuits such as programmable multiplexers.

摘要翻译： 不对称晶体管，例如不对称传输晶体管可以形成在集成电路上。 不对称晶体管可以具有栅极结构。 可以在每个晶体管栅极结构的相对侧上的源极漏极中形成对称的袋状植入物。 选择性加热可用于不对称地扩散植入物。 可以通过在半导体衬底上图案化栅极结构来实现选择性加热，使得相邻栅极结构之间的间隔变化。 给定的栅极结构可以位于与给定栅极结构不同的相应距离处间隔开的第一和第二相邻栅极结构之间。 较大的栅极结构间隔导致比较小栅极结构间隔更大的衬底温度升高。 在较大的温度上升的情况下，口袋植入物在衬底的部分扩散，产生不对称晶体管。 不对称传输晶体管可以由来自存储器元件的静态控制信号来控制，以实现诸如可编程多路复用器之类的电路。

公开(公告)号：US08633731B1

公开(公告)日：2014-01-21

申请号：US13206401

申请日：2011-08-09

申请人： Irfan Rahim ,  Mao Du ,  Jeffrey Xiaoqi Tung ,  Jun Liu ,  Qi Xiang

发明人： Irfan Rahim ,  Mao Du ,  Jeffrey Xiaoqi Tung ,  Jun Liu ,  Qi Xiang

IPC分类号： G06F7/38

CPC分类号： H03K19/1733 ,  G11C8/16 ,  G11C11/419

摘要： Integrated circuits such as programmable integrated circuits may have configuration random-access memory elements. The configuration random-access memory elements may be loaded with configuration data to customize programmable circuitry on the integrated circuits. Each memory element may have a bistable element that is powered using a positive power supply voltage and a negative power supply voltage. Programmable transistors in the programmable circuitry may have gates coupled to outputs of the bistable elements. The programmable transistors may have gate insulators that are thinner than gate insulators in the transistors of the bistable elements and may have threshold voltages of about zero volts. During operation, some of the configuration random-access memory elements may supply negative voltages to their associated programmable transistors so that the programmable transistors are provided with gate-source voltages of less than zero volts.

摘要翻译： 诸如可编程集成电路的集成电路可以具有配置随机存取存储器元件。 配置随机存取存储器元件可以被加载配置数据以定制集成电路上的可编程电路。 每个存储元件可以具有使用正电源电压和负电源电压供电的双稳态元件。 可编程电路中的可编程晶体管可以具有耦合到双稳态元件的输出的栅极。 可编程晶体管可以具有比双稳态元件的晶体管中的栅极绝缘体更薄的栅极绝缘体，并且可以具有约零伏特的阈值电压。 在操作期间，一些配置随机存取存储器元件可以向其相关联的可编程晶体管提供负电压，使得可编程晶体管具有小于零伏的栅极 - 源极电压。

公开(公告)号：US20120235662A1

公开(公告)日：2012-09-20

申请号：US13051648

申请日：2011-03-18

申请人： Albert Ratnakumar ,  Qi Xiang ,  Simardeep Maangat ,  Jun Liu

发明人： Albert Ratnakumar ,  Qi Xiang ,  Simardeep Maangat ,  Jun Liu

IPC分类号： G05F3/02

CPC分类号： G05F3/30

摘要： A low-voltage reference circuit may have a pair of semiconductor devices. Each semiconductor device may have an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator interposed between the metal gate and the n-type semiconductor region through which carriers tunnel. The metal gate may have a work function matching that of p-type polysilicon. The gate insulator may have a thickness of less than about 25 angstroms. The metal gate may form a first terminal for the semiconductor device and the n+ region and n-type semiconductor region may form a second terminal for the semiconductor device. The second terminals may be coupled to ground. A biasing circuit may use the first terminals to supply different currents to the semiconductor devices and may provide a corresponding reference output voltage at a value that is less than one volt.

摘要翻译： 低压参考电路可以具有一对半导体器件。 每个半导体器件可以具有n型半导体区域，n型半导体区域中的n +区域，金属栅极和介于金属栅极和n型半导体区域之间的栅极绝缘体，载流子穿过该栅极绝缘体。 金属栅极可以具有与p型多晶硅相匹配的功函数。 栅极绝缘体可以具有小于约25埃的厚度。 金属栅极可以形成用于半导体器件的第一端子，并且n +区域和n型半导体区域可以形成用于半导体器件的第二端子。 第二端子可以接地。 偏置电路可以使用第一端子来向半导体器件提供不同的电流，并且可以将相应的参考输出电压提供在小于1伏的值。

公开(公告)号：US08242581B1

公开(公告)日：2012-08-14

申请号：US12324793

申请日：2008-11-26

申请人： Albert Ratnakumar ,  Wilson Wong ,  Jun Liu ,  Qi Xiang ,  Jeffrey Xiaoqi Tung

发明人： Albert Ratnakumar ,  Wilson Wong ,  Jun Liu ,  Qi Xiang ,  Jeffrey Xiaoqi Tung

IPC分类号： H01L29/93

CPC分类号： H01L29/94 ,  H01L29/4983 ,  H01L29/93

摘要： Mixed gate varactors are provided. The mixed gate varactors may include a semiconductor region of a given doping type. A first terminal for the varactor may be formed from a gate structure on the semiconductor region. A second terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has the same doping type as the given doping type. A third terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has a different doping type than the given doping type. The gate structure may include multiple gate conductors on a gate insulator. The gate insulator may be a high-K dielectric. The gate conductors may be metals or other materials that have different work functions. A conductive layer such as a layer of polysilicon may electrically connect the first and second gate conductors.

摘要翻译： 提供混合栅极变容二极管。 混合栅极变容二极管可以包括给定掺杂型的半导体区域。 用于变容二极管的第一端可以由半导体区域上的栅极结构形成。 用于变容二极管的第二端子可以由具有与给定掺杂类型相同的掺杂类型的半导体区域中的重掺杂区域形成。 用于变容二极管的第三端子可以由具有与给定掺杂类型不同的掺杂类型的半导体区域中的重掺杂区域形成。 栅极结构可以包括栅极绝缘体上的多个栅极导体。 栅极绝缘体可以是高K电介质。 栅极导体可以是具有不同功函数的金属或其它材料。 诸如多晶硅层的导电层可电连接第一和第二栅极导体。

公开(公告)号：US08530976B1

公开(公告)日：2013-09-10

申请号：US13113896

申请日：2011-05-23

申请人： Albert Ratnakumar ,  Qi Xiang ,  Jun Liu

发明人： Albert Ratnakumar ,  Qi Xiang ,  Jun Liu

IPC分类号： H01L21/70

CPC分类号： H01L29/7833 ,  H01L21/823842 ,  H01L27/1104

摘要： Integrated circuits may be provided that include memory elements that produce output control signals and corresponding programmable logic circuitry that receives the output control signals from the memory elements. The memory elements may include bistable storage elements formed from circuits such as cross-coupled inverters. The inverters may include n-channel metal-oxide-semiconductor transistors with p-metal gate conductors and n-channel metal-oxide-semiconductor transistors with p-metal gate conductors. These gate conductor assignments are the reverse of the gate conductor assignments used in the n-channel and p-channel transistors in other circuitry such as the programmable logic circuitry. The reversed gate conductor assignments increase the threshold voltages of the transistors in the memory elements to improve reliability in scenarios in which the memory elements are overdriving pass transistors in the programmable logic circuitry.

摘要翻译： 可以提供集成电路，其包括产生输出控制信号的存储器元件和从存储器元件接收输出控制信号的相应的可编程逻辑电路。 存储器元件可以包括由诸如交叉耦合的反相器的电路形成的双稳态存储元件。 反相器可以包括具有p金属栅极导体的n沟道金属氧化物半导体晶体管和具有p型金属栅极导体的n沟道金属氧化物半导体晶体管。 这些栅极导体分配与在诸如可编程逻辑电路的其它电路中的n沟道和p沟道晶体管中使用的栅极导体分配相反。 反向栅极导体分配增加存储器元件中的晶体管的阈值电压，以提高存储元件过驱动可编程逻辑电路中的通过晶体管的情况下的可靠性。

公开(公告)号：US08264214B1

公开(公告)日：2012-09-11

申请号：US13051648

申请日：2011-03-18

申请人： Albert Ratnakumar ,  Qi Xiang ,  Simardeep Maangat ,  Jun Liu

发明人： Albert Ratnakumar ,  Qi Xiang ,  Simardeep Maangat ,  Jun Liu

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： A low-voltage reference circuit may have a pair of semiconductor devices. Each semiconductor device may have an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator interposed between the metal gate and the n-type semiconductor region through which carriers tunnel. The metal gate may have a work function matching that of p-type polysilicon. The gate insulator may have a thickness of less than about 25 angstroms. The metal gate may form a first terminal for the semiconductor device and the n+ region and n-type semiconductor region may form a second terminal for the semiconductor device. The second terminals may be coupled to ground. A biasing circuit may use the first terminals to supply different currents to the semiconductor devices and may provide a corresponding reference output voltage at a value that is less than one volt.

摘要翻译： 低压参考电路可以具有一对半导体器件。 每个半导体器件可以具有n型半导体区域，n型半导体区域中的n +区域，金属栅极和介于金属栅极和n型半导体区域之间的栅极绝缘体，载流子穿过该栅极绝缘体。 金属栅极可以具有与p型多晶硅相匹配的功函数。 栅极绝缘体可以具有小于约25埃的厚度。 金属栅极可以形成用于半导体器件的第一端子，并且n +区域和n型半导体区域可以形成用于半导体器件的第二端子。 第二端子可以接地。 偏置电路可以使用第一端子来向半导体器件提供不同的电流，并且可以将相应的参考输出电压提供在小于1伏的值。