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公开(公告)号：US6103607A
公开(公告)日：2000-08-15
申请号：US153522
申请日：1998-09-15
IPC分类号： H01L29/78 , C23C14/06 , H01L21/28 , H01L21/285 , H01L21/336 , H01L29/49 , H01L21/3205 , H01L21/4763
CPC分类号： C23C14/0617 , C23C14/0641 , H01L21/28097 , H01L29/4975
摘要： The specification describes a process for making gate electrodes for silicon MOS transistor devices. The gate electrode is a composite of a first layer of tungsten suicide, a second layer of tungsten silicide nitride, and a third layer of tungsten silicide. The absence of polysilicon as a main constituent of the gate electrode eliminates depletion effects. The presence of nitride in the composite gate electrode impedes updiffusion of boron from the source and drain. The layers are preferably formed in situ in an PVD apparatus.
摘要翻译： 该说明书描述了用于制造硅MOS晶体管器件的栅电极的工艺。 栅电极是第一层硅化钨，第二层硅化钨和第三层硅化钨的复合材料。 不存在多晶硅作为栅电极的主要成分消除了耗尽效应。 复合栅电极中氮化物的存在阻止了硼从源极和漏极的更多扩散。 这些层优选在PVD装置中原位形成。
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公开(公告)号：US06358790B1
公开(公告)日：2002-03-19
申请号：US09250501
申请日：1999-02-16
IPC分类号： H01L218234
CPC分类号： H01L28/60 , H01L21/3212 , H01L21/32136 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/90
摘要： The present invention provides a method for fabricating a capacitor, comprising the steps of forming a trench in a substrate, forming a layer of a first material selected from the group consisting of titanium and titanium nitride in the trench, filling the trench with a conductive material to form a plug, planarizing the substrate, patterning the substrate to expose the first material, forming an electrode material layer over the substrate, and patterning the electrode material layer, whereby the first material is substantially encapsulated by the electrode material layer.
摘要翻译： 本发明提供一种制造电容器的方法，包括以下步骤：在衬底中形成沟槽，在沟槽中形成从由钛和氮化钛组成的组中选择的第一材料的层，用导电材料填充沟槽 以形成插头，使衬底平坦化，图案化衬底以露出第一材料，在衬底上形成电极材料层，以及图案化电极材料层，由此第一材料基本上被电极材料层封装。
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公开(公告)号：US06331484B1
公开(公告)日：2001-12-18
申请号：US09519193
申请日：2000-03-06
IPC分类号： H01L214763
CPC分类号： H01L21/76864 , H01L21/76807 , H01L21/76841 , H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A titanium-tantalum barrier layer film for use in conjunction with an interconnect film such as copper and a method for forming the same provides a relatively titanium rich/tantalum deficient portion adjacent the interface it forms with a dielectric film and a relatively tantalum rich/titanium deficient portion adjacent the interface it forms with a conductive interconnect film formed over the barrier layer film. The titanium rich/tantalum deficient portion provides good adhesion to the dielectric film and the tantalum rich/titanium deficient portion forms a hetero-epitaxial interface with the interconnect film and suppresses the formation of inter-metallic compounds. A single titanium-tantalum film having a composition gradient from top-to-bottom may be formed using various techniques including PVD, CVD, sputter deposition using a sputtering target of homogeneous composition, and sputter deposition using multiple sputtering targets. A composite titanium-tantalum film consists of two separately formed films.
摘要翻译： 用于与诸如铜的互连膜一起使用的钛 - 钽阻挡层膜及其形成方法提供了与其形成的界面相邻的富钛/钽缺陷部分，其与介电膜和相对富钽/钛 与其形成的界面相邻的缺陷部分与在阻挡层膜上形成的导电互连膜形成。 富钛/钽缺陷部分对电介质膜提供良好的粘附性，并且富钽/钛缺陷部分与互连膜形成异质外延界面并抑制金属间化合物的形成。 可以使用包括PVD，CVD，使用均匀组合物的溅射靶的溅射沉积以及使用多个溅射靶的溅射沉积的各种技术来形成具有从顶部到底部的组成梯度的单个钛 - 钽膜。 复合钛 - 钽薄膜由两个单独形成的薄膜组成。
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公开(公告)号：US06319837B1
公开(公告)日：2001-11-20
申请号：US09606833
申请日：2000-06-29
IPC分类号： H01L2100
CPC分类号： H01L21/7684
摘要： The present invention includes a method for reducing dishing of an integrated circuit interconnect, comprising the steps of providing excess interconnect material above a damascene feature in a substrate and planarizing the substrate and interconnect material to obtain an interconnect in the substrate.
摘要翻译： 本发明包括一种用于减少集成电路互连的凹陷的方法，包括以下步骤：在衬底上的镶嵌特征之上提供过量的互连材料，并平坦化衬底和互连材料以获得衬底中的互连。
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5.发明授权Colloidal suspension of abrasive particles containing magnesium as CMP slurry 有权含有镁的磨料颗粒的胶体悬浮液作为CMP浆料公开(公告)号：US06319095B1
公开(公告)日：2001-11-20
申请号：US09521768
申请日：2000-03-09
IPC分类号： B24B100
CPC分类号： C09K3/1463 , B24B37/044 , C09G1/02
摘要： An improved colloidal slurry for chemical mechanical polishing and methods of polishing using the improved colloidal slurry.
摘要翻译： 用于化学机械抛光的改进的胶体浆料和使用改进的胶体浆料的抛光方法。
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公开(公告)号：US06291848B1
公开(公告)日：2001-09-18
申请号：US09364767
申请日：1999-07-30
申请人： Sundar Srinivasan Chetlur , James Theodore Clemens , Sailesh Mansinh Merchant , Pradip Kumar Roy , Hem M. Vaidya
发明人： Sundar Srinivasan Chetlur , James Theodore Clemens , Sailesh Mansinh Merchant , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： H01L27108
CPC分类号： H01L21/76838 , H01L27/10817 , H01L27/10852 , H01L28/60
摘要： An integrated circuit capacitor includes a substrate, a first dielectric layer adjacent the substrate and having a first trench therein, and a first metal plug extending upwardly into the first trench. An interconnection line overlies the first trench and contacts the first metal plug to define anchoring recesses on opposite sides of the first metal plug. A second dielectric layer is on the interconnection line and has a second trench therein. A second metal plug extends upwardly into the second trench. More particularly, the second metal plug includes a body portion extending upwardly into the second trench, and anchor portions connected to the body portion and engaging the anchoring recesses to anchor the second metal plug to the interconnection line. Because the second metal plug is anchored, a depth of the second trench can be greater without the metal plug becoming loose and separating from the underlying interconnection line.
摘要翻译： 集成电路电容器包括衬底，与衬底相邻并且在其中具有第一沟槽的第一电介质层和向上延伸到第一沟槽中的第一金属插塞。 互连线覆盖在第一沟槽上并接触第一金属插塞以在第一金属插塞的相对侧上限定锚定凹槽。 第二介电层位于互连线上并且在其中具有第二沟槽。 第二金属插头向上延伸到第二沟槽中。 更具体地，第二金属插头包括向上延伸到第二沟槽中的主体部分，以及连接到主体部分并且与固定凹部接合并将第二金属插头固定到互连线的锚定部分。 由于第二金属插塞被锚固，所以第二沟槽的深度可以更大，而不会使金属插头松动并与下面的互连线分离。
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7.发明授权Method of forming in-situ electroplated oxide passivating film for corrosion inhibition 失效形成原位电镀氧化钝化膜的方法进行腐蚀抑制公开(公告)号：US06524957B2
公开(公告)日：2003-02-25
申请号：US09953706
申请日：2001-09-17
IPC分类号： H01L2144
CPC分类号： H01L21/76877 , H01L21/76834 , H01L21/7684 , H01L21/76888 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method an apparatus for making copper metallic interconnects for semiconductors having an oxide layer deposited in the copper in situ during the deposition of the copper within the via.
摘要翻译： 一种用于制造用于半导体的铜金属互连的装置，该铜金属互连件在铜在通孔内沉积期间具有在原位沉积在铜中的氧化物层。
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8.发明授权CMP system and slurry for polishing semiconductor wafers and related method 有权CMP系统和用于抛光半导体晶片的浆料及相关方法公开(公告)号：US06364744B1
公开(公告)日：2002-04-02
申请号：US09496829
申请日：2000-02-02
IPC分类号： B24B4900
CPC分类号： B24B37/04 , B24B57/02 , C09G1/02 , C09K3/1463 , H01L21/3212
摘要： A chemical mechanical polishing (CMP) system includes a polishing device including a polishing article. The polishing device provides relative movement between the semiconductor wafer and the polishing article with a slurry therebetween. The slurry preferably includes abrasive particles and a photocatalyst to enhance oxidation of metal of the semiconductor wafer. The slurry may also include water and the photocatalyst is a mixed metal oxide for breaking down water into hydrogen and oxygen in the presence of light.
摘要翻译： 化学机械抛光（CMP）系统包括包括抛光制品的抛光装置。 抛光装置提供半导体晶片和抛光制品之间的相对运动，其间具有浆料。 该浆料优选包括研磨颗粒和光催化剂以增强半导体晶片的金属的氧化。 浆料还可以包括水，光催化剂是用于在光存在下将水分解成氢和氧的混合金属氧化物。
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公开(公告)号：US06287970B1
公开(公告)日：2001-09-11
申请号：US09370912
申请日：1999-08-06
IPC分类号： H01L2144
CPC分类号： H01L21/76877 , H01L21/321 , H01L21/76886
摘要： A method of making a semiconductor device includes the steps of forming an oxide layer adjacent a semiconductor substrate, etching trenches within the oxide layer, depositing a copper layer to at least fill the etched trenches, and forming a copper arsenate layer on the deposited copper layer. The copper arsenate layer is then chemically mechanically polished. The copper layer may be deposited by at least one of electrodeposition, electroplating and chemical vapor deposition. The copper arsenate layer on the surface of the deposited copper layer inhibits oxidation and corrosion and stabilizes the microstructure of the deposited copper layer to thereby eliminate a need to subsequently anneal the deposited copper layer.
摘要翻译： 制造半导体器件的方法包括以下步骤：在半导体衬底附近形成氧化物层，蚀刻氧化物层内的沟槽，沉积铜层以至少填充蚀刻的沟槽，以及在沉积的铜层上形成砷酸铜层 。 然后将砷酸铜层化学机械抛光。 可以通过电沉积，电镀和化学气相沉积中的至少一种来沉积铜层。 沉积的铜层表面上的砷酸铜层抑制氧化和腐蚀并稳定沉积的铜层的微观结构，从而不需要随后退火沉积的铜层。
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10.发明授权Methods of fabricating an integrated circuit device with composite oxide dielectric 有权制造具有复合氧化物电介质的集成电路器件的方法公开(公告)号：US06235594B1
公开(公告)日：2001-05-22
申请号：US09340224
申请日：1999-06-25
IPC分类号： H01L21336
CPC分类号： H01L28/56 , H01L21/28194 , H01L27/1085 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A method of fabricating an integrated circuit device includes forming a first metal oxide layer adjacent a semiconductor substrate. The first metal oxide layer may be formed of tantalum oxide, for example. A second metal oxide layer, which includes an oxide with a relatively high dielectric constant such as titanium oxide, zirconium oxide, or ruthenium oxide, is formed on the first metal oxide layer opposite the semiconductor substrate, and a metal nitride layer, such as titanium nitride, is formed on the metal oxide layer opposite the first metal oxide layer. The metal nitride layer includes a metal which is capable of reducing the metal oxide of the first metal oxide layer. Thus, the second metal oxide layer substantially blocks reduction of the metal oxide of the first metal oxide layer by the metal of the metal nitride layer.
摘要翻译： 制造集成电路器件的方法包括：形成与半导体衬底相邻的第一金属氧化物层。 第一金属氧化物层例如可以由氧化钽形成。 在与半导体衬底相对的第一金属氧化物层上形成第二金属氧化物层，其包含氧化钛，氧化锆或氧化钌等介电常数较高的氧化物，金属氮化物层如钛 在与第一金属氧化物层相对的金属氧化物层上形成氮化物。 金属氮化物层包括能够还原第一金属氧化物层的金属氧化物的金属。 因此，第二金属氧化物层通过金属氮化物层的金属基本上阻止第一金属氧化物层的金属氧化物的还原。
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