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    Hardware-based messaging appliance
    2.
    发明申请
    Hardware-based messaging appliance 审中-公开
    基于硬件的消息收发设备

    公开(公告)号：US20060168070A1

    公开(公告)日：2006-07-27

    申请号：US11317295

    申请日：2005-12-23

    申请人： J. Thompson ,  Kul Singh ,  Pierre Fraval

    发明人： J. Thompson ,  Kul Singh ,  Pierre Fraval

    IPC分类号： G06F15/16

    CPC分类号： G06Q10/00 ,  G06F9/542 ,  G06F9/546 ,  G06F2209/544 ,  H04L12/1895 ,  H04L41/0806 ,  H04L41/082 ,  H04L41/0879 ,  H04L41/0886 ,  H04L41/5009 ,  H04L43/06 ,  H04L43/0817 ,  H04L43/0852 ,  H04L43/0894 ,  H04L51/00 ,  H04L51/14 ,  H04L67/24 ,  H04L67/2852 ,  H04L67/322 ,  H04L67/327 ,  H04L69/18 ,  H04L69/40

    摘要： Message publish/subscribe systems are required to process high message volumes with reduced latency and performance bottlenecks. The hardware-based messaging appliance proposed by the present invention is designed for high-volume, low-latency messaging. The hardware-based messaging appliance is part of a publish/subscribe middleware system. With the hardware-based messaging appliances, this system operates to, among other things, reduce intermediary hops with neighbor-based routing, introduce efficient native-to-external and external-to-native protocol conversions, monitor system performance, including latency, in real time, employ topic-based and channel-based message communications, and dynamically optimize system interconnect configurations and message transmission protocols.

    摘要翻译： 消息发布/订阅系统需要处理高消息量，降低延迟和性能瓶颈。 本发明提出的基于硬件的消息收发设备被设计用于高容量，低延迟的消息传送。 基于硬件的消息传递设备是发布/订阅中间件系统的一部分。 使用基于硬件的消息传递设备，该系统除了其他功能之外还可以减少具有基于邻居路由的中间跳跃，引入高效的本地到外部和外部到本地的协议转换，监控系统性能（包括延迟） 实时，采用基于主题和基于通道的消息通信，并动态优化系统互连配置和消息传输协议。

    Systems and methods for the implementation of a core schema for providing a top-level structure for organizing units of information manageable by a hardware/software interface system
    3.
    发明申请
    Systems and methods for the implementation of a core schema for providing a top-level structure for organizing units of information manageable by a hardware/software interface system 有权
    用于实现核心模式的系统和方法，用于提供用于组织由硬件/软件接口系统管理的信息单元的顶级结构

    公开(公告)号：US20050050053A1

    公开(公告)日：2005-03-03

    申请号：US10646632

    申请日：2003-08-21

    申请人： J. Thompson

    发明人： J. Thompson

    IPC分类号： G06F7/00 ,  G06F12/00 ,  G06F13/00 ,  G06F17/00 ,  G11B5/00

    CPC分类号： G06F17/30595 ,  Y10S707/99935 ,  Y10S707/99943 ,  Y10S707/99944 ,  Y10S707/99945

    摘要： Various embodiments of the present invention are directed to a method, in a computer system, for a hardware/software interface system to manipulate a plurality of discrete units of information having properties understandable by said hardware/software interface system (“Items”), said method comprising the use of a core schema to define a set of core Items which said hardware/software interface system understands and can directly process in a predetermined and predictable way. The core Items are derived from the base Item type. In certain embodiments, the Items types in the core schema cannot be directly subtyped but may instead be extended to incorporate additional properties in specific contexts without becoming inconsistent in other contexts that only comprehend the core Item type.

    摘要翻译： 本发明的各种实施例涉及一种在计算机系统中用于硬件/软件接口系统来操纵具有由所述硬件/软件接口系统（“项目”）可理解的属性的多个信息的离散单元的方法，所述方法 方法包括使用核心模式来定义所述硬件/软件接口系统理解并可以以预定和可预测的方式直接处理的一组核心项目。 核心项目来自基础项目类型。 在某些实施例中，核心模式中的Items类型不能被直接子类型化，而是可以扩展以在特定上下文中并入另外的属性，而不会在仅了解核心项目类型的其他上下文中变得不一致。

    Metal during pattern for memory devices
    4.
    发明申请
    Metal during pattern for memory devices 审中-公开

    公开(公告)号：US20070096324A1

    公开(公告)日：2007-05-03

    申请号：US11641896

    申请日：2006-12-20

    申请人： J. Thompson ,  Todd Merritt

    发明人： J. Thompson ,  Todd Merritt

    IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

    CPC分类号： H01L27/10882 ,  G11C5/025 ,  G11C5/063 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on the third layer with non-I/O lines adapted to reduce interference between I/O lines. Column select lines, orthogonal to I/O lines and disposed in the third layer of metallic traces, except in the vicinity of I/O lines, are provided in a linear configuration and shielded from parallel digit lines in the first layer of traces by traces of the intervening second layer of traces. Global bleeder lines disposed in the third layer of traces are adapted to apply a standby voltage to a plurality of sense amplifiers. Other features of the invention include two layer power and ground bus traces, and row decoder and phase driver circuits disposed in throat and gap cell regions respectively.

    Systems and methods for separating units of information manageable by a hardware/software interface system from their physical organization
    6.
    发明申请
    Systems and methods for separating units of information manageable by a hardware/software interface system from their physical organization 有权
    用于将由硬件/软件接口系统管理的信息的单元与其物理组织分离的系统和方法

    公开(公告)号：US20050055380A1

    公开(公告)日：2005-03-10

    申请号：US10646941

    申请日：2003-08-21

    申请人： J. Thompson ,  Kim Cameron ,  Srinivasmurthy Acharya ,  Balan Raman

    发明人： J. Thompson ,  Kim Cameron ,  Srinivasmurthy Acharya ,  Balan Raman

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30233 ,  G06F17/30286 ,  Y10S707/99944

    摘要： Various embodiments of the present invention are directed to a hardware/software interface system for a computer system for manipulating a plurality of discrete units of information at a hardware/software interface system level (“Items”), said Items interconnected by Relationships and where Items have Relationships to other Items. One such relationship between Items may be for the purposes of logically denoting to the hardware/software interface system wether one Item is public and accessible or private and unaccessible to another Item.

    摘要翻译： 本发明的各种实施例涉及一种用于计算机系统的硬件/软件接口系统，用于在硬件/软件接口系统级别（“项目”）处操作多个离散的信息单元，所述由关系互连的项目以及项目 与其他项目有关系。 项目之间的一个这样的关系可能是为了在逻辑上表示硬件/软件界面系统的目的，一个项目是公开的，可访问的或私有的，并且不可访问另一个项目。

    Metal during pattern for memory devices
    7.
    发明申请
    Metal during pattern for memory devices 审中-公开
    存储器件模式中的金属

    公开(公告)号：US20070096323A1

    公开(公告)日：2007-05-03

    申请号：US11641895

    申请日：2006-12-20

    申请人： J. Thompson ,  Todd Merritt

    发明人： J. Thompson ,  Todd Merritt

    IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

    CPC分类号： H01L27/10882 ,  G11C5/025 ,  G11C5/063 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on the third layer with non-I/O lines adapted to reduce interference between I/O lines. Column select lines, orthogonal to I/O lines and disposed in the third layer of metallic traces, except in the vicinity of I/O lines, are provided in a linear configuration and shielded from parallel digit lines in the first layer of traces by traces of the intervening second layer of traces. Global bleeder lines disposed in the third layer of traces are adapted to apply a standby voltage to a plurality of sense amplifiers. Other features of the invention include two layer power and ground bus traces, and row decoder and phase driver circuits disposed in throat and gap cell regions respectively.

    摘要翻译： 一种存储器集成电路，其具有布置在包括各种有源器件的衬底组件之上的三层金属迹线。 迹线被布置成包括在第三层中连续的I / O迹线跨过阵列的4或8个存储块，并且散布在第三层上，其中非I / O线适于减少I之间的干扰 / O线。 与I / O线正交并且布置在除了I / O线附近的第三层金属迹线中的列选择线被提供为线性配置，并且通过迹线屏蔽在第一层迹线中的平行数字线 的第二层痕迹。 设置在第三层迹线中的全局放电线适于将待机电压施加到多个读出放大器。 本发明的其它特征包括分别设置在喉部和间隙细胞区域中的两层电力和地面总线迹线以及行解码器和相位驱动电路。

    Memory architecture
    8.
    发明申请
    Memory architecture 有权
    内存架构

    公开(公告)号：US20060245231A1

    公开(公告)日：2006-11-02

    申请号：US11476744

    申请日：2006-06-29

    申请人： J. Thompson ,  Jeffrey Wright ,  Victor Wong ,  Jim Cullum

    发明人： J. Thompson ,  Jeffrey Wright ,  Victor Wong ,  Jim Cullum

    IPC分类号： G11C5/06

    CPC分类号： G11C7/1066 ,  G11C5/025 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C8/12 ,  G11C11/4085 ,  G11C11/4093

    摘要： A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays. The unidirectional row logic is located in the outward periphery of its associated array, but is not within a throat region between two arrays. The location of the row logic allows the throat region to include more bidirectional IO circuitry and signal lines servicing two arrays, which increases the performance of the SDRAM. In addition, separate power bussing is employed for the memory arrays and IO circuitry. This prevents noise from the arrays from affecting the IO circuitry and signal lines of the throat region and vice versa.

    摘要翻译： DDR SDRAM，其中单向行逻辑与单个存储器阵列相关联并连接到单个存储器阵列，而不是与多个存储器阵列相关联并连接到多个存储器阵列。 单向行逻辑位于其关联阵列的外围，但不在两个阵列之间的喉部区域内。 行逻辑的位置允许喉部区域包括更多的双向IO电路和服务两个阵列的信号线，这增加了SDRAM的性能。 此外，存储器阵列和IO电路采用单独的功率总线。 这可以防止阵列的噪声影响喉部区域的IO电路和信号线，反之亦然。

    End-to-end publish/subscribe middleware architecture
    9.
    发明申请
    End-to-end publish/subscribe middleware architecture 有权
    端到端发布/订阅中间件架构

    公开(公告)号：US20060149840A1

    公开(公告)日：2006-07-06

    申请号：US11316778

    申请日：2005-12-23

    申请人： J. Thompson ,  Kul Singh ,  Pierre Fraval

    发明人： J. Thompson ,  Kul Singh ,  Pierre Fraval

    IPC分类号： G06F15/173

    CPC分类号： H04L67/02 ,  H04L12/1859 ,  H04L43/06 ,  H04L43/0852 ,  H04L45/24 ,  H04L47/11 ,  H04L47/15 ,  H04L47/70 ,  H04L47/801 ,  H04L47/806 ,  H04L47/822 ,  H04L47/829 ,  H04L67/26 ,  H04L67/327

    摘要： Message publish/subscribe systems are required to process high message volumes with reduced latency and performance bottlenecks. The end-to-end middleware architecture proposed by the present invention is designed for high-volume, low-latency messaging by, among other things, reducing intermediary hops with neighbor-based routing, introducing efficient native-to-external and external-to-native protocol conversions, monitoring system performance, including latency, in real time, employing topic-based and channel-based message communications, and dynamically optimizing system interconnect configurations and message transmission protocols.

    摘要翻译： 消息发布/订阅系统需要处理高消息量，降低延迟和性能瓶颈。 本发明提出的端对端中间件架构被设计用于大容量，低延迟的消息传送，其中除其他之外，通过基于邻居的路由减少中间跳，将本地到外部和外部的有效地引入到 实时协议转换，监控系统性能，包括实时延迟，采用基于主题和基于通道的消息通信，以及动态优化系统互连配置和消息传输协议。

    Metal wiring pattern for memory devices
    10.
    发明申请
    Metal wiring pattern for memory devices 审中-公开

    公开(公告)号：US20060141765A1

    公开(公告)日：2006-06-29

    申请号：US11359467

    申请日：2006-02-23

    申请人： J. Thompson ,  Todd Merritt

    发明人： J. Thompson ,  Todd Merritt

    IPC分类号： H01L21/4763 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8242

    CPC分类号： H01L27/10882 ,  G11C5/025 ,  G11C5/063 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on the third layer with non-I/O lines adapted to reduce interference between I/O lines. Column select lines, orthogonal to I/O lines and disposed in the third layer of metallic traces, except in the vicinity of I/O lines, are provided in a linear configuration and shielded from parallel digit lines in the first layer of traces by traces of the intervening second layer of traces. Global bleeder lines disposed in the third layer of traces are adapted to apply a standby voltage to a plurality of sense amplifiers. Other features of the invention include two layer power and ground bus traces, and row decoder and phase driver circuits disposed in throat and gap cell regions respectively.