摘要:
A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.
摘要:
A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.
摘要:
A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.
摘要:
A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.
摘要:
A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.
摘要:
A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.
摘要:
A lateral double-gate FET structure with sub-lithographic source and drain regions is disclosed. The sub-lithographic source and drain regions are defined by a sacrificial spacer. Self-aligned metal-semiconductor alloy and metal contacts are made to the sub-lithographic source and drain using conventional silicon processing.
摘要:
A lateral double-gate FET structure with sub-lithographic source and drain regions is disclosed. The sub-lithographic source and drain regions are defined by a sacrificial spacer. Self-aligned metal-semiconductor alloy and metal contacts are made to the sub-lithographic source and drain using conventional silicon processing.
摘要:
A lateral double-gate FET structure with sub-lithographic source and drain regions is disclosed. The sub-lithographic source and drain regions are defined by a sacrificial spacer. Self-aligned metal-semiconductor alloy and metal contacts are made to the sub-lithographic source and drain using conventional silicon processing.
摘要:
A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.