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1.发明授权Method and apparatus for generating from a single supply line voltages internal to a flash memory with reduced settling times 有权用于从单个电源线产生闪存的内部电压降低的稳定时间的方法和装置公开(公告)号：US06392936B1
公开(公告)日：2002-05-21
申请号：US09608239
申请日：2000-06-30
申请人： Jacopo Mulatti , Marco Maccarrone
发明人： Jacopo Mulatti , Marco Maccarrone
IPC分类号： G11C1300
摘要： Presented is a memory architecture including at least first, second and third voltage booster circuits adapted to generate, on respective first, second and third circuit nodes, at least first, second and third boosted voltage references. These boosted references are in turn connected to first, second and third adjusters, which are adapted to provide respective first, second and third voltage references as required for the operations of programming, erasing and verifying cells of the memory architecture. At least a first switch block is used that connects between the first and third circuit nodes and is controlled by a first control signal to place the first and third high-voltage references in parallel during cell verify operations, thereby to provide one equivalent high-voltage source having a higher capacity for current than individual sources and effectively speed up the charging of the first circuit node so as to shorten the settling time of the first voltage reference. A method is also presented for generating voltage references with a reduced value of settling time as produced within a memory architecture.
摘要翻译： 提出了一种存储器架构，其包括至少第一，第二和第三升压电路，其适于在相应的第一，第二和第三电路节点上产生至少第一，第二和第三升压电压基准。 这些升压参考依次连接到第一，第二和第三调节器，其适于提供针对存储器结构的编程，擦除和验证单元的操作所需的相应的第一，第二和第三电压基准。 至少使用连接在第一和第三电路节点之间的第一开关块，并且由第一控制信号控制，以在单元验证操作期间并行地布置第一和第三高压基准，从而提供一个等效的高电压 源具有比单个源更高的电流容量，并且有效地加速第一电路节点的充电，以便缩短第一参考电压的建立时间。 还提出了一种用于产生具有在存储器架构内产生的建立时间的降低的值的电压基准的方法。
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2.发明授权公开(公告)号：US06266222B1
公开(公告)日：2001-07-24
申请号：US09223621
申请日：1998-12-30
IPC分类号： H02H904
CPC分类号： H01L27/0259 , H01L27/0251
摘要： An ESD protection network protects a CMOS circuit structure integrated in a semiconductor substrate. The circuit structure includes discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply having a respective primary ground, and from at least one secondary voltage supply having a respective secondary ground. This network includes a first ESD protection element for an input stage of the circuit structure; a second ESD protection element for an output stage of the circuit structure, the first and second protection elements having an input/output pad of the integrated circuit structure in common; a first ESD protection element between the primary supply and the primary ground; and a second ESD protection element between the secondary supply and the secondary ground.
摘要翻译： ESD保护网络保护集成在半导体衬底中的CMOS电路结构。 电路结构包括形成在相应的衬底部分中的分立电路块，它们彼此电绝缘并且由至少一个具有各自的初级接地的初级电压源以及至少一个具有相应次级接地的次级电压源独立供电。 该网络包括用于电路结构的输入级的第一ESD保护元件; 用于所述电路结构的输出级的第二ESD保护元件，所述第一和第二保护元件具有所述集成电路结构的输入/输出焊盘; 主要供电和主地面之间的第一个ESD保护元件; 以及在次级电源和次级接地之间的第二ESD保护元件。
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公开(公告)号：US5859797A
公开(公告)日：1999-01-12
申请号：US846753
申请日：1997-04-30
CPC分类号： G11C16/30
摘要： A circuit for generating biasing signals in reading of a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type and having a control terminal and a conduction terminal to be biased, as well as MOS transistors connecting the memory element with a reference low supply voltage comprises a voltage booster for generating a first voltage output signal to be applied to the control terminal of the memory element and a limitation network for the voltage signal connected to the output of the voltage booster. There is also provided a circuit portion for generating a second voltage output signal to be applied to the control terminal of one of the above mentioned transistors. This circuit portion comprises a timing section interlocked with the voltage booster of a section generating the second voltage signal.
摘要翻译： 一种用于在读入包括EPROM或闪存类型的至少一个存储元件并具有要偏置的控制端子和导电端子的冗余UPROM单元的电路中产生偏置信号的电路，以及连接存储元件与参考电压的MOS晶体管 低电源电压包括用于产生要施加到存储元件的控制端的第一电压输出信号的电压升压器和连接到升压器的输出的电压信号的限制网络。 还提供了用于产生要施加到上述晶体管之一的控制端子的第二电压输出信号的电路部分。 该电路部分包括与产生第二电压信号的部分的升压器互锁的定时部分。
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4.发明授权Method and a device for measuring an analog voltage in a non-volatile memory 有权用于测量非易失性存储器中的模拟电压的方法和装置公开(公告)号：US06507183B1
公开(公告)日：2003-01-14
申请号：US09608847
申请日：2000-06-29
申请人： Jacopo Mulatti , Marco Maccarrone
发明人： Jacopo Mulatti , Marco Maccarrone
IPC分类号： G01R1706
CPC分类号： G11C29/02 , G11C16/04 , G11C16/30 , G11C29/50 , G11C2029/5004
摘要： Presented is an analog voltage value measuring device for measuring any of a set of voltage references that are generated inside a memory architecture. The selected voltage to be measured is connected to a facility line through a multiplexer. The memory architecture includes a set of output buffers connected to a respective set of output pads. The device also includes a converter block, connected between the facility line and the output buffers of the memory architecture for converting a measured analog value of a voltage reference selected by the multiplexer to a digital value, which is presented on the output pads. A method of measuring an analog voltage value in a memory device is also disclosed. The method includes selecting an analog voltage value from the set of voltage values; transferring the selected analog value onto the facility line; converting the selected analog value to a digital value; and presenting the digital value on the output pads.
摘要翻译： 提出了一种模拟电压值测量装置，用于测量在存储器架构内产生的一组电压基准的任何一个。 所选择的被测电压通过多路复用器连接到设备线。 存储器架构包括连接到相应的一组输出焊盘的一组输出缓冲器。 该设备还包括一个连接在设备线路和存储器结构的输出缓冲器之间的转换器模块，用于将由多路复用器选择的电压基准测量的模拟值转换成在输出焊盘上呈现的数字值。 还公开了一种测量存储器件中的模拟电压值的方法。 该方法包括从该组电压值中选择模拟电压值; 将所选择的模拟值传送到设备线上; 将所选择的模拟值转换为数字值; 并在输出板上显示数字值。
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公开(公告)号：US06307396B1
公开(公告)日：2001-10-23
申请号：US09231130
申请日：1998-12-30
IPC分类号： H03K190185
CPC分类号： H03K19/0016
摘要： A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference. Advantageously, the first inverter in the chain includes a means of selecting the delivery path to the stage according to an activate signal for a low-consumption operation mode. In essence, the first inverter of the buffer has two signal paths: one for normal operation and the other for low consumption operation.
摘要翻译： 低功耗TTL-CMOS输入缓冲级包括串联的反相器链，其串联在接收TTL逻辑电平的电信号的输入端和CMOS逻辑电平的输出再现电信号之间，并且在第一或电源电压基准和 第二或地面参考。 有利地，链中的第一反相器包括根据低功耗操作模式的激活信号选择到载物台的输送路径的装置。 实质上，缓冲器的第一个反相器具有两个信号路径：一个用于正常操作，另一个用于低功耗操作。
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公开(公告)号：US08582364B2
公开(公告)日：2013-11-12
申请号：US13155347
申请日：2011-06-07
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G06F1/28 , G06F3/0619 , G06F3/0625 , G06F3/0653 , G06F3/0688 , G06F12/0802 , G06F13/4282 , G06F2212/222 , G06F2213/0032 , G11C16/0483 , G11C16/14 , G11C16/26 , G11C16/28 , G11C16/30 , Y02D10/14 , Y02D10/151
摘要： In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.
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公开(公告)号：US20110235411A1
公开(公告)日：2011-09-29
申请号：US13155347
申请日：2011-06-07
CPC分类号： G11C16/10 , G06F1/28 , G06F3/0619 , G06F3/0625 , G06F3/0653 , G06F3/0688 , G06F12/0802 , G06F13/4282 , G06F2212/222 , G06F2213/0032 , G11C16/0483 , G11C16/14 , G11C16/26 , G11C16/28 , G11C16/30 , Y02D10/14 , Y02D10/151
摘要： In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.
摘要翻译： 在包括存储器单元矩阵的存储器件的实施例中，其中存储器单元布置在多个存储器单元串中，每个存储单元串包括至少两个串联的存储器单元，至少两个存储器单元串的组被连接到 并且其中所述存储器单元适于被编程为至少第一编程状态和第二编程状态，存储数据的方法包括利用用于写入数据的每个存储器单元串的单个存储器单元， 其中所述利用包括使单个存储器单元进入第二编程状态，所述串的剩余存储单元保持在第一编程状态。
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公开(公告)号：US5650671A
公开(公告)日：1997-07-22
申请号：US379689
申请日：1995-01-27
申请人： Luigi Pascucci , Marco Maccarrone , Silvia Padoan
发明人： Luigi Pascucci , Marco Maccarrone , Silvia Padoan
摘要： A charge pump circuit including a number of pull-up stages connected in parallel with one another between a reference potential line and an output line. Each stage includes a capacitor having a first terminal connected to a charging and discharging node, and a second terminal connected to a pull-up node for switching between a first charging operating phase and a second charge transferring operating phase. The charging and discharging node is connected to the supply line via a charging transistor having a control terminal connected to a high-voltage bias node formed by the adjacent stage in the opposite operating phase, for charging the capacitor substantially up to the supply voltage.
摘要翻译： 一种电荷泵电路，包括在参考电位线和输出线之间彼此并联连接的多个上拉级。 每个级包括具有连接到充电和放电节点的第一端子的电容器，以及连接到上拉节点的第二端子，用于在第一充电操作阶段和第二充电转移操作阶段之间切换。 充电和放电节点通过充电晶体管连接到电源线，该充电晶体管具有在相反的工作阶段中由相邻级形成的高压偏置节点连接的控制端子，用于对电容器充电至基本上达到电源电压。
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公开(公告)号：US5594703A
公开(公告)日：1997-01-14
申请号：US365510
申请日：1994-12-28
申请人： Marco Olivo , Marco Maccarrone
发明人： Marco Olivo , Marco Maccarrone
CPC分类号： H03K21/38
摘要： An end-of-count detecting device for nonvolatile memories, comprising a decoder in the form of a wired OR structure of a number of transistors of the same type, the gate terminals of which are fed with a count signal generated by a counter element and having a predetermined end-of-count value to be detected. A load, which may be static, pseudo-dynamic or dynamic, is provided between the common node of the decoder transistors and a reference potential line; and the decoder output formed by the common node assumes a different logic level according to whether or not the end-of-count value coded by the wired OR structure is reached. A number of wired OR structures may be arranged side by side with an array of transistors for detecting a number of end-of-count values of the same counter element.
摘要翻译： 一种用于非易失性存储器的计数结束检测装置，包括具有相同类型的多个晶体管的有线OR结构形式的解码器，其栅极端被馈送由计数器元件产生的计数信号， 具有要检测的预定计数结束值。 在解码晶体管的公共节点和参考电位线之间提供可以是静态的，伪动态的或动态的负载; 并且由公共节点形成的解码器输出根据是否达到由有线OR结构编码的计数结束值而呈现不同的逻辑电平。 多个有线OR结构可以并排布置有用于检测相同计数器元件的计数结束值的数量的晶体管阵列。
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10.发明授权Integrated programming circuitry for an electrically programmable semiconductor memory device with redundancy 失效用于具有冗余的电可编程半导体存储器件的集成编程电路
公开(公告)号：US5548554A
公开(公告)日：1996-08-20
申请号：US365154
申请日：1994-12-28
申请人： Luigi Pascucci , Silvia Padoan , Marco Maccarrone
发明人： Luigi Pascucci , Silvia Padoan , Marco Maccarrone
CPC分类号： G11C29/70
摘要： An integrated programming circuitry for an electrically programmable semiconductor memory device comprises a plurality of programming load circuits, each one associated with a respective memory matrix portion or group of columns, and a plurality of programming load control circuits, each one controlling the activation of one respective programming load circuit according to the logic state of a respective data line carrying a datum to be programmed; the memory device comprises a group of redundancy bit lines and an associated redundancy programming load circuit; each programming load control circuit comprises decoding means supplied with signals which, when a defective column address is supplied to the memory device during programming, are generated from a matrix portion identifying code stored in a non-volatile register wherein the defective column address is stored, and switch means responsive to a decoded signal at the output of said decoding means to enable the activation of the redundancy programming load circuit according to the logic state of the data signal line and to cause the inhibition of the activation of the respective programming load circuit.
摘要翻译： 用于电可编程半导体存储器件的集成编程电路包括多个编程负载电路，每个编程负载电路各自与相应的存储器矩阵部分或一组列相关联，以及多个编程负载控制电路，每个编程负载控制电路控制一个相应的激活 根据携带要编程的数据的相应数据线的逻辑状态编程负载电路; 存储器件包括一组冗余位线和相关的冗余编程负载电路; 每个编程负载控制电路包括提供有信号的解码装置，当在编程期间将缺陷列地址提供给存储器件时，从存储在存储有缺陷列地址的非易失性寄存器中的矩阵部分识别代码生成信号， 以及响应于所述解码装置的输出处的解码信号的开关装置，以使能根据数据信号线的逻辑状态激活冗余编程负载电路，并且导致禁止各个编程负载电路的激活。
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