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1.发明授权公开(公告)号：US06266222B1
公开(公告)日：2001-07-24
申请号：US09223621
申请日：1998-12-30
IPC分类号： H02H904
CPC分类号： H01L27/0259 , H01L27/0251
摘要： An ESD protection network protects a CMOS circuit structure integrated in a semiconductor substrate. The circuit structure includes discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply having a respective primary ground, and from at least one secondary voltage supply having a respective secondary ground. This network includes a first ESD protection element for an input stage of the circuit structure; a second ESD protection element for an output stage of the circuit structure, the first and second protection elements having an input/output pad of the integrated circuit structure in common; a first ESD protection element between the primary supply and the primary ground; and a second ESD protection element between the secondary supply and the secondary ground.
摘要翻译： ESD保护网络保护集成在半导体衬底中的CMOS电路结构。 电路结构包括形成在相应的衬底部分中的分立电路块，它们彼此电绝缘并且由至少一个具有各自的初级接地的初级电压源以及至少一个具有相应次级接地的次级电压源独立供电。 该网络包括用于电路结构的输入级的第一ESD保护元件; 用于所述电路结构的输出级的第二ESD保护元件，所述第一和第二保护元件具有所述集成电路结构的输入/输出焊盘; 主要供电和主地面之间的第一个ESD保护元件; 以及在次级电源和次级接地之间的第二ESD保护元件。
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2.发明授权Method and apparatus for generating from a single supply line voltages internal to a flash memory with reduced settling times 有权用于从单个电源线产生闪存的内部电压降低的稳定时间的方法和装置公开(公告)号：US06392936B1
公开(公告)日：2002-05-21
申请号：US09608239
申请日：2000-06-30
申请人： Jacopo Mulatti , Marco Maccarrone
发明人： Jacopo Mulatti , Marco Maccarrone
IPC分类号： G11C1300
摘要： Presented is a memory architecture including at least first, second and third voltage booster circuits adapted to generate, on respective first, second and third circuit nodes, at least first, second and third boosted voltage references. These boosted references are in turn connected to first, second and third adjusters, which are adapted to provide respective first, second and third voltage references as required for the operations of programming, erasing and verifying cells of the memory architecture. At least a first switch block is used that connects between the first and third circuit nodes and is controlled by a first control signal to place the first and third high-voltage references in parallel during cell verify operations, thereby to provide one equivalent high-voltage source having a higher capacity for current than individual sources and effectively speed up the charging of the first circuit node so as to shorten the settling time of the first voltage reference. A method is also presented for generating voltage references with a reduced value of settling time as produced within a memory architecture.
摘要翻译： 提出了一种存储器架构，其包括至少第一，第二和第三升压电路，其适于在相应的第一，第二和第三电路节点上产生至少第一，第二和第三升压电压基准。 这些升压参考依次连接到第一，第二和第三调节器，其适于提供针对存储器结构的编程，擦除和验证单元的操作所需的相应的第一，第二和第三电压基准。 至少使用连接在第一和第三电路节点之间的第一开关块，并且由第一控制信号控制，以在单元验证操作期间并行地布置第一和第三高压基准，从而提供一个等效的高电压 源具有比单个源更高的电流容量，并且有效地加速第一电路节点的充电，以便缩短第一参考电压的建立时间。 还提出了一种用于产生具有在存储器架构内产生的建立时间的降低的值的电压基准的方法。
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公开(公告)号：US5859797A
公开(公告)日：1999-01-12
申请号：US846753
申请日：1997-04-30
CPC分类号： G11C16/30
摘要： A circuit for generating biasing signals in reading of a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type and having a control terminal and a conduction terminal to be biased, as well as MOS transistors connecting the memory element with a reference low supply voltage comprises a voltage booster for generating a first voltage output signal to be applied to the control terminal of the memory element and a limitation network for the voltage signal connected to the output of the voltage booster. There is also provided a circuit portion for generating a second voltage output signal to be applied to the control terminal of one of the above mentioned transistors. This circuit portion comprises a timing section interlocked with the voltage booster of a section generating the second voltage signal.
摘要翻译： 一种用于在读入包括EPROM或闪存类型的至少一个存储元件并具有要偏置的控制端子和导电端子的冗余UPROM单元的电路中产生偏置信号的电路，以及连接存储元件与参考电压的MOS晶体管 低电源电压包括用于产生要施加到存储元件的控制端的第一电压输出信号的电压升压器和连接到升压器的输出的电压信号的限制网络。 还提供了用于产生要施加到上述晶体管之一的控制端子的第二电压输出信号的电路部分。 该电路部分包括与产生第二电压信号的部分的升压器互锁的定时部分。
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4.发明授权Method and a device for measuring an analog voltage in a non-volatile memory 有权用于测量非易失性存储器中的模拟电压的方法和装置公开(公告)号：US06507183B1
公开(公告)日：2003-01-14
申请号：US09608847
申请日：2000-06-29
申请人： Jacopo Mulatti , Marco Maccarrone
发明人： Jacopo Mulatti , Marco Maccarrone
IPC分类号： G01R1706
CPC分类号： G11C29/02 , G11C16/04 , G11C16/30 , G11C29/50 , G11C2029/5004
摘要： Presented is an analog voltage value measuring device for measuring any of a set of voltage references that are generated inside a memory architecture. The selected voltage to be measured is connected to a facility line through a multiplexer. The memory architecture includes a set of output buffers connected to a respective set of output pads. The device also includes a converter block, connected between the facility line and the output buffers of the memory architecture for converting a measured analog value of a voltage reference selected by the multiplexer to a digital value, which is presented on the output pads. A method of measuring an analog voltage value in a memory device is also disclosed. The method includes selecting an analog voltage value from the set of voltage values; transferring the selected analog value onto the facility line; converting the selected analog value to a digital value; and presenting the digital value on the output pads.
摘要翻译： 提出了一种模拟电压值测量装置，用于测量在存储器架构内产生的一组电压基准的任何一个。 所选择的被测电压通过多路复用器连接到设备线。 存储器架构包括连接到相应的一组输出焊盘的一组输出缓冲器。 该设备还包括一个连接在设备线路和存储器结构的输出缓冲器之间的转换器模块，用于将由多路复用器选择的电压基准测量的模拟值转换成在输出焊盘上呈现的数字值。 还公开了一种测量存储器件中的模拟电压值的方法。 该方法包括从该组电压值中选择模拟电压值; 将所选择的模拟值传送到设备线上; 将所选择的模拟值转换为数字值; 并在输出板上显示数字值。
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公开(公告)号：US06307396B1
公开(公告)日：2001-10-23
申请号：US09231130
申请日：1998-12-30
IPC分类号： H03K190185
CPC分类号： H03K19/0016
摘要： A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference. Advantageously, the first inverter in the chain includes a means of selecting the delivery path to the stage according to an activate signal for a low-consumption operation mode. In essence, the first inverter of the buffer has two signal paths: one for normal operation and the other for low consumption operation.
摘要翻译： 低功耗TTL-CMOS输入缓冲级包括串联的反相器链，其串联在接收TTL逻辑电平的电信号的输入端和CMOS逻辑电平的输出再现电信号之间，并且在第一或电源电压基准和 第二或地面参考。 有利地，链中的第一反相器包括根据低功耗操作模式的激活信号选择到载物台的输送路径的装置。 实质上，缓冲器的第一个反相器具有两个信号路径：一个用于正常操作，另一个用于低功耗操作。
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6.发明授权Circuit and method for generating a read reference signal for nonvolatile memory cells 失效用于产生用于非易失性存储单元的读取参考信号的电路和方法
公开(公告)号：US5805500A
公开(公告)日：1998-09-08
申请号：US877921
申请日：1997-06-18
CPC分类号： G11C16/28
摘要： The current flowing through a cell to be read, forming part of a nonvolatile memory array and presenting a characteristic with a predetermined slope, is amplified N times and compared with a reference current presenting a two portion characteristic: a first portion extending between a predetermined threshold value and a trigger value, and presenting a slope equal to that of the memory cell characteristic, and a second portion extending from the trigger value, and presenting a slope amplified N times with respect to that of the cell characteristic and therefore equal to the amplified slope of the cell.
摘要翻译： 流过待读取的单元的电流，形成非易失性存储器阵列的一部分并呈现具有预定斜率的特性，被放大N倍，并与呈现两部分特性的参考电流进行比较：在预定阈值之间延伸的第一部分 值和触发值，并且呈现与存储器单元特性相同的斜率，以及从触发值延伸的第二部分，并且呈现相对于单元特性的N倍的斜率，因此等于放大的 细胞斜率
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7.发明授权Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory 有权用于产生ATD信号以调节对非易失性存储器的访问的方法和电路
公开(公告)号：US6075750A
公开(公告)日：2000-06-13
申请号：US186497
申请日：1998-11-04
CPC分类号： G11C8/18
摘要： A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells. The method consists of duplicating the ATD signal into at least one pair of signals and propagating such signals through separate parallel timing chains at the ends of which the ATD signal is reinstated, the chains being alternately active.
摘要翻译： 一种方法和电路产生用于对半导体集成电子存储器件中的存储单元读取相位进行定时的脉冲同步信号（ATD）。 在检测到存储器单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD）。 该方法包括将ATD信号复制到至少一对信号中，并且通过在ATD信号被恢复的端部处的分离的并行定时链传播这样的信号，链条交替活跃。
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8.发明授权Read circuit and method for nonvolatile memory cells with an equalizing structure 失效具有均衡结构的非易失性存储单元的读取电路和方法
公开(公告)号：US5886925A
公开(公告)日：1999-03-23
申请号：US877922
申请日：1997-06-18
CPC分类号： G11C16/28
摘要： The read circuit presents a current mirror circuit including a first and second load transistor interposed between the supply line and a respective first and second output node. The first output node is connected to a cell to be read, the second output node is connected to a generating stage generating a reference current having a predetermined characteristic, and the size of the second load transistor is N times greater than the first load transistor. To permit rapid cell reading even in the presence of low supply voltage and with no initial uncertainty, an equalizing circuit presents a current balancing branch connected between the first output node and ground for generating an equalizing current presenting a ratio of 1/N with the reference current to balance the circuit before commencing the reading.
摘要翻译： 读取电路提供电流镜电路，其包括插入在电源线和相应的第一和第二输出节点之间的第一和第二负载晶体管。 第一输出节点连接到要读取的单元，第二输出节点连接到产生具有预定特性的参考电流的发生级，并且第二负载晶体管的尺寸大于第一负载晶体管的N倍。 为了即使在低电源电压并且没有初始不确定性的情况下也允许快速电池读取，均衡电路提供连接在第一输出节点和地之间的电流平衡支路，用于产生与参考值1 / N的比率的均衡电流 电流在开始读数之前平衡电路。
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9.发明授权Driving circuit with three output levels, one output level being a boosted level 有权驱动电路具有三个输出电平，一个输出电平为提升电平
公开(公告)号：US06157225A
公开(公告)日：2000-12-05
申请号：US234016
申请日：1999-01-19
IPC分类号： G11C8/08 , H03K19/0185 , H03K17/10
CPC分类号： H03K19/018585 , G11C8/08
摘要： A driving circuit supplied by a supply voltage and a reference voltage, generates an output signal and comprises a first circuit adapted to selectively couple the output signal to the reference voltage or to an internal voltage line internal to the driving circuit in response to a first control signal. The driving circuit also includes a switching circuit adapted to selectively couple the internal voltage line to the supply voltage. A boosting circuit is connected to the internal voltage line and is adapted to bring the internal voltage line to a boosted voltage. The switching circuit and the boosting circuit are controlled by a second control signal to be alternatively activatable, in such a way to bring the internal voltage line either to the supply voltage or to the boosted voltage.
摘要翻译： 由电源电压和参考电压提供的驱动电路产生输出信号，并且包括适于选择性地将输出信号耦合到参考电压的第一电路或响应于第一控制的驱动电路内部的内部电压线 信号。 驱动电路还包括适于选择性地将内部电压线耦合到电源电压的开关电路。 升压电路连接到内部电压线，并且适于使内部电压线达到升压电压。 开关电路和升压电路由第二控制信号控制，以备可激活的方式，以使内部电压线达到供电电压或升压电压。
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公开(公告)号：US08582364B2
公开(公告)日：2013-11-12
申请号：US13155347
申请日：2011-06-07
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G06F1/28 , G06F3/0619 , G06F3/0625 , G06F3/0653 , G06F3/0688 , G06F12/0802 , G06F13/4282 , G06F2212/222 , G06F2213/0032 , G11C16/0483 , G11C16/14 , G11C16/26 , G11C16/28 , G11C16/30 , Y02D10/14 , Y02D10/151
摘要： In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.
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