利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

44 条记录 (耗时 0.022 秒)

    Method of forming a self-aligned contact pad for a semiconductor device
    1.
    发明授权
    Method of forming a self-aligned contact pad for a semiconductor device 有权
    形成用于半导体器件的自对准接触焊盘的方法

    公开(公告)号：US06355547B1

    公开(公告)日：2002-03-12

    申请号：US09645968

    申请日：2000-08-24

    申请人： Jae-Goo Lee ,  Chang-Hyun Cho ,  Gwan-Hyeob Koh

    发明人： Jae-Goo Lee ,  Chang-Hyun Cho ,  Gwan-Hyeob Koh

    IPC分类号： H01L23209

    CPC分类号： H01L27/10873 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888

    摘要： A method of manufacturing a self-aligned contact pad for the fabrication of an integrated circuit is disclosed. A plurality of gate structures is formed on the substrate. A first insulating layer is formed over the plurality of gate structures. Then, a second insulating layer is formed over the first insulating layer and filling spaces between the gate structures. Next, a portion of second insulating layer is removed between the gate structures, thereby forming a plurality of contact holes between the gate structures and exposing a portion of the first insulating layer. The exposed portion of the first insulating layer is etched away to form a gate spacer on the sidewalls of the gate structures and exposing surfaces of active regions of the substrate. Finally, the plurality of contact holes are filled with a first conductive layer and the first conductive layer is planarized to form contact pads.

    摘要翻译： 公开了一种用于制造集成电路的自对准接触焊盘的制造方法。 在基板上形成多个栅极结构。 在多个栅极结构上形成第一绝缘层。 然后，在第一绝缘层上形成第二绝缘层，并在栅极结构之间填充空间。 接下来，在栅极结构之间移除第二绝缘层的一部分，从而在栅极结构之间形成多个接触孔，并露出第一绝缘层的一部分。 蚀刻掉第一绝缘层的暴露部分，以在栅极结构的侧壁和衬底的有源区域的暴露表面上形成栅极间隔物。 最后，多个接触孔填充有第一导电层，并且第一导电层被平坦化以形成接触焊盘。

    Method of fabricating MOS transistors
    3.
    发明授权
    Method of fabricating MOS transistors 有权
    制造MOS晶体管的方法

    公开(公告)号：US06753227B2

    公开(公告)日：2004-06-22

    申请号：US10437881

    申请日：2003-05-13

    申请人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Ki-Nam Kim

    发明人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Ki-Nam Kim

    IPC分类号： H01L21336

    CPC分类号： H01L21/823807 ,  H01L21/28061 ,  H01L21/823892 ,  H01L29/4933

    摘要： A method of fabricating a MOS transistor is provided. According to the method, a rapid thermal anneal is applied to a semiconductor substrate having active regions doped with well impurity ions and channel impurity ions. Thus, during implantation of the well and the channel impurity ions, crystalline defects resulting from the implantation can be cured by the rapid thermal anneal.

    摘要翻译： 提供一种制造MOS晶体管的方法。 根据该方法，将快速热退火应用于具有掺杂有良好杂质离子和沟道杂质离子的有源区的半导体衬底。 因此，在注入阱和通道杂质离子期间，通过快速热退火可以固化由植入产生的结晶缺陷。

    Method for fabricating MOS transistor
    4.
    发明授权
    Method for fabricating MOS transistor 失效
    制造MOS晶体管的方法

    公开(公告)号：US06335233B1

    公开(公告)日：2002-01-01

    申请号：US09347822

    申请日：1999-07-02

    申请人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Mi-Hyang Lee ,  Dae-Won Ha

    发明人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Mi-Hyang Lee ,  Dae-Won Ha

    IPC分类号： H01L218238

    CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/7833

    摘要： A first conductive impurity ion is implanted into a semiconductor substrate to form a well area on which a gate electrode is formed. A first non-conductive impurity is implanted into the well area on both sides of the gate electrode to control a substrate defect therein and to form a first precipitate area to a first depth. A second conductive impurity ion is implanted into the well area on both sides of the gate electrode, so that a source/drain area is formed to a second depth being relatively shallower than the first depth. A second non-conductive impurity is implanted into the source/drain area so as to control a substrate defect therein and to form a second precipitate area. As a result, substrate defects such as dislocation, extended defect, and stacking fault are isolated from a P-N junction area, thereby forming a stable P-N junction.

    摘要翻译： 将第一导电杂质离子注入到半导体衬底中以形成其上形成栅电极的阱区。 将第一非导电杂质注入到栅极两侧的阱区中以控制其中的衬底缺陷并形成第一深度的第一沉淀区。 将第二导电杂质离子注入到栅极两侧的阱区中，使得源/漏区形成为比第一深度相对浅的第二深度。 将第二非导电杂质注入源/漏区，以便控制其中的衬底缺陷并形成第二沉淀区。 结果，从P-N结区域隔离诸如位错，延伸缺陷和堆垛层错的基板缺陷，从而形成稳定的P-N结。

    Semiconductor device including storage node and method of manufacturing the same
    5.
    发明授权
    Semiconductor device including storage node and method of manufacturing the same 有权
    包括存储节点的半导体器件及其制造方法

    公开(公告)号：US07180118B2

    公开(公告)日：2007-02-20

    申请号：US10830895

    申请日：2004-04-22

    申请人： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

    发明人： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10891 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/91

    摘要： A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.

    摘要翻译： 一种包括存储节点的半导体器件及其制造方法，该方法包括在半导体衬底上形成绝缘层和蚀刻停止层; 通过穿透所述绝缘层和所述蚀刻停止层形成要与所述半导体衬底电连接的存储节点接触体; 在所述蚀刻停止层上形成分别电连接到所述存储节点接触体的着陆焊盘; 以及分别在着陆焊盘上形成存储节点，其外侧壁完全暴露的存储节点和彼此成角度地布置。

    Method for forming a self aligned contact in a semiconductor device
    6.
    发明授权
    Method for forming a self aligned contact in a semiconductor device 有权
    在半导体器件中形成自对准接触的方法

    公开(公告)号：US06337275B1

    公开(公告)日：2002-01-08

    申请号：US09334669

    申请日：1999-06-17

    申请人： Chang-Hyun Cho ,  Kyu-Hyun Lee ,  Jae-Goo Lee ,  Sang-Sup Jeong

    发明人： Chang-Hyun Cho ,  Kyu-Hyun Lee ,  Jae-Goo Lee ,  Sang-Sup Jeong

    IPC分类号： H01L2144

    CPC分类号： H01L21/76897 ,  H01L21/76834

    摘要： A self aligned contact (SAC) pad in a semiconductor device and a method for forming thereof wherein an SAC opening is formed concurrently with single-layer gate spacers. After formation of the stacked gate pattern having a gate electrode and a capping layer disposed thereon, an insulating layer for gate spacers is deposited thereon. An interlayer insulating layer then is deposited over the insulating layer. The interlayer insulating layer has an etch selectivity with respect to the capping layer and insulating layer. SAC then are opened in the interlayer insulating layer while concurrently forming single-layer gate spacers.

    摘要翻译： 半导体器件中的自对准接触（SAC）焊盘及其形成方法，其中SAC开口与单层栅极间隔物同时形成。 在形成具有设置在其上的栅电极和覆盖层的堆叠栅极图案之后，在其上沉积栅极间隔物的绝缘层。 然后在绝缘层上沉积层间绝缘层。 层间绝缘层相对于覆盖层和绝缘层具有蚀刻选择性。 然后在层间绝缘层中打开SAC，同时形成单层栅极间隔物。

    Method of forming self-aligned contact pads on electrically conductive lines
    7.
    发明授权
    Method of forming self-aligned contact pads on electrically conductive lines 有权
    在导电线上形成自对准接触焊盘的方法

    公开(公告)号：US06268252B1

    公开(公告)日：2001-07-31

    申请号：US09442523

    申请日：1999-11-18

    申请人： Jae-Goo Lee ,  Chang-Hyun Cho

    发明人： Jae-Goo Lee ,  Chang-Hyun Cho

    IPC分类号： H01L21336

    CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76895 ,  H01L24/05 ,  H01L2924/14 ,  H01L2924/00

    摘要： Self aligned contact pads in a semiconductor device and a method for forming thereof wherein etching back process is carried out on the contact pad comprising material and insulating layer down to the top surface of a capping layer of a gate electrode, and also portions of the capping layer is selectively etched with respect to the contact pad composing material at the end of the etching back process and thereby forming the contact pads to be electrically separated from each other. SAC is opened by etching insulating layer selectively to the capping layer using SAC gate mask. A conductive material as for SAC pad is deposited over the insulating layer to fill the SAC opening. Etching back process is carried out to form the SAC pad.

    摘要翻译： 半导体器件中的自对准接触焊盘及其形成方法，其中在包括材料和绝缘层的接触焊盘上进行蚀刻回加工，直到栅电极的覆盖层的顶表面，以及封盖的部分 在蚀刻返回处理结束时相对于接触焊盘构成材料选择性地蚀刻层，从而形成彼此电分离的接触焊盘。 使用SAC栅极掩模，通过将绝缘层选择性地蚀刻到覆盖层来打开SAC。 用于SAC焊盘的导电材料沉积在绝缘层上以填充SAC开口。 进行蚀刻处理以形成SAC焊盘。

    Semiconductor device including storage node and method of manufacturing the same
    8.
    发明授权
    Semiconductor device including storage node and method of manufacturing the same 有权
    包括存储节点的半导体器件及其制造方法

    公开(公告)号：US07476585B2

    公开(公告)日：2009-01-13

    申请号：US11621507

    申请日：2007-01-09

    申请人： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

    发明人： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

    IPC分类号： H01L21/8239

    CPC分类号： H01L27/10891 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/91

    摘要： A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.

    摘要翻译： 一种包括存储节点的半导体器件及其制造方法，该方法包括在半导体衬底上形成绝缘层和蚀刻停止层; 通过穿透所述绝缘层和所述蚀刻停止层形成要与所述半导体衬底电连接的存储节点接触体; 在所述蚀刻停止层上形成分别电连接到所述存储节点接触体的着陆焊盘; 以及分别在着陆焊盘上形成存储节点，其外侧壁完全暴露的存储节点和彼此成角度地布置。

    Methods of forming self-aligned contact pads on electrically conductive lines
    9.
    发明授权
    Methods of forming self-aligned contact pads on electrically conductive lines 有权
    在导电线上形成自对准接触焊盘的方法

    公开(公告)号：US06465310B2

    公开(公告)日：2002-10-15

    申请号：US09892125

    申请日：2001-06-26

    申请人： Jae-Goo Lee ,  Chang-Hyun Cho

    发明人： Jae-Goo Lee ,  Chang-Hyun Cho

    IPC分类号： H01L21336

    CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76895 ,  H01L24/05 ,  H01L2924/14 ,  H01L2924/00

    摘要： Self aligned contact pads in a semicondductor device and a method for forming thereof within etching back process is carried out on the contact pad comprising material and insulating layer down to the top surface of a capping layer of a gate electrode, and also portions of the capping layer is selectively etched with respect to the contact pad composing material at the end of the etching back process and thereby forming the contact pads to be electrically separated from each other. SAC is opened by etching insulating layer selectively to the capping layer using SAC gate mask. A conductive material as for SAC pad is deposited over the insulating layer to fill the SAC opening. Etching back process is carried out to form the SAC pad.

    摘要翻译： 在半导体器件中的自对准接触焊盘及其在回蚀工艺中形成的方法在包括材料和绝缘层的接触焊盘上进行到栅电极的覆盖层的顶表面，还有部分封盖 在蚀刻返回处理结束时相对于接触焊盘构成材料选择性地蚀刻层，从而形成彼此电分离的接触焊盘。 使用SAC栅极掩模，通过将绝缘层选择性地蚀刻到覆盖层来打开SAC。 用于SAC焊盘的导电材料沉积在绝缘层上以填充SAC开口。 进行蚀刻处理以形成SAC焊盘。