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    Method for fabricating semiconductor device with self-aligned storage node
    1.
    发明授权
    Method for fabricating semiconductor device with self-aligned storage node 失效
    用于制造具有自对准存储节点的半导体器件的方法

    公开(公告)号：US06838341B2

    公开(公告)日：2005-01-04

    申请号：US10688079

    申请日：2003-10-16

    申请人： Jae-Man Yoon ,  Yun-Jae Lee ,  Sang-Hyun Lee ,  Wook-Je Kim

    发明人： Jae-Man Yoon ,  Yun-Jae Lee ,  Sang-Hyun Lee ,  Wook-Je Kim

    IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10814 ,  H01L21/76802 ,  H01L21/76897 ,  H01L27/10855 ,  H01L28/91

    摘要： A method for fabricating a semiconductor device includes preparing a semiconductor substrate having a contact pad; forming a first insulating film having a storage node contact exposing the contact pad and having a stack structure of an upper interlayer insulating film, a bottom interlayer insulating film, and an etching stopper between the upper and bottom interlayer insulating layers that protrudes into the storage node contact; forming a first conductive film for a storage node on the substrate; forming a second insulating film where a portion of a surface corresponding to the storage node contact is recessed; forming an etching mask layer on the recessed portion of the second insulating film; etching the second insulating film using the etching mask layer; forming a second conductive film for a storage node on the substrate; etching the first and second conductive films to isolate nodes; and removing the etching mask layer, the second insulating film and the upper interlayer insulating film.

    Method of forming a reliable high performance capacitor using an isotropic etching process
    2.
    发明授权
    Method of forming a reliable high performance capacitor using an isotropic etching process 有权
    使用各向同性蚀刻工艺形成可靠的高性能电容器的方法

    公开(公告)号：US07101769B2

    公开(公告)日：2006-09-05

    申请号：US10776546

    申请日：2004-02-10

    申请人： Seung-Beom Kim ,  Won-Mo Park ,  Yun-Jae Lee ,  Joon-Mo Kwon ,  Myoung-Hee Han ,  Man-Jong Yu

    发明人： Seung-Beom Kim ,  Won-Mo Park ,  Yun-Jae Lee ,  Joon-Mo Kwon ,  Myoung-Hee Han ,  Man-Jong Yu

    IPC分类号： H01L21/20

    CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852

    摘要： Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.

    摘要翻译： 本文公开了一种使用各向同性蚀刻工艺形成可靠的高性能电容器的方法，以优化下电极的表面积，同时防止在下电极之间形成电桥。 该方法包括在衬底上形成的多个牺牲氧化物层，具有接触插塞的绝缘层和蚀刻停止层。 将牺牲氧化物层图案化并另外进行各向同性蚀刻以形成扩大的电容器孔。 然后蚀刻停止层的暴露部分以形成露出接触插塞的上部和与其相邻的绝缘层的一部分的最终电容器孔。 清洁具有最终电容器孔的半导体衬底以去除接触插塞的暴露的上部上的自然氧化膜。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20120139021A1

    公开(公告)日：2012-06-07

    申请号：US13241435

    申请日：2011-09-23

    申请人： Seok-Hyun Kim ,  Deok-Sung Hwang ,  Yun-Jae Lee ,  Chul Lee ,  Yoon-Taek Jang ,  Chang-Hoon Jeon ,  Sang-Bin Ahn ,  Jun-Hyeok Ahn

    发明人： Seok-Hyun Kim ,  Deok-Sung Hwang ,  Yun-Jae Lee ,  Chul Lee ,  Yoon-Taek Jang ,  Chang-Hoon Jeon ,  Sang-Bin Ahn ,  Jun-Hyeok Ahn

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10876 ,  H01L21/765

    摘要： A semiconductor memory device includes a transistor having a channel region buried in a substrate and source/drain regions formed to provide low contact resistance. A field isolation structure is formed in the substrate to define active structures. The field isolation structure includes a gap-fill pattern, a first material layer surrounding the gap-fill pattern, and a second material layer surrounding at least a portion of the first material layer. Each active structure includes a first active pattern having a top surface located beneath the level of the top surface of the field isolation structure, and a second active pattern disposed on the first active pattern and whose top is located above the level of the top surface of the field isolation structure.

    摘要翻译： 半导体存储器件包括具有掩埋在衬底中的沟道区和形成为提供低接触电阻的源极/漏极区的晶体管。 在衬底中形成场隔离结构以限定有源结构。 场隔离结构包括间隙填充图案，围绕间隙填充图案的第一材料层和围绕第一材料层的至少一部分的第二材料层。 每个有源结构包括第一有源图案，其具有位于场隔离结构的顶表面的平面下方的顶表面，以及布置在第一有源图案上的第二有源图案，其顶部位于第一有源图案的顶表面的高度之上 现场隔离结构。

    Method of fabricating a semiconductor device
    4.
    发明授权
    Method of fabricating a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06221778B1

    公开(公告)日：2001-04-24

    申请号：US09368166

    申请日：1999-08-05

    申请人： Yun-Jae Lee

    发明人： Yun-Jae Lee

    IPC分类号： H01L21311

    CPC分类号： H01L29/6659 ,  H01L21/31116 ,  H01L21/76834

    摘要： A method of fabricating semiconductor device, which reduces amount of oxidization on semiconductor substrate to suppress volume expansion of an active region of a semiconductor substrate, thereby removing pits on the semiconductor substrate. A conductive layer for forming a gate electrode and a first insulating layer serving as a mask are sequentially formed on the semiconductor substrate. Using a mask for forming a gate electrode, the first insulating layer and the conductive layer are sequentially etched to form a gate electrode. A second insulating layer and a third insulating layer are formed on the structure of the gate electrode and the surface of the semiconductor substrate. A third insulating layer formed on an overall surface of the semiconductor substrate is dry etched to form an insulating layer spacer on sidewalls of the gate electrode. A fourth insulating layer is formed on the structure of the semiconductor substrate and the gate electrode by a deposition process. That is, after forming an insulating layer spacer on sidewalls of the gate electrode, an oxide layer is formed by a deposition process so as to compensate for damage.

    摘要翻译： 一种制造半导体器件的方法，其减少半导体衬底上的氧化量，以抑制半导体衬底的有源区的体积膨胀，从而去除半导体衬底上的凹坑。 用于形成栅电极的导电层和用作掩模的第一绝缘层依次形成在半导体衬底上。 使用用于形成栅电极的掩模，依次蚀刻第一绝缘层和导电层以形成栅电极。 在栅电极的结构和半导体衬底的表面上形成第二绝缘层和第三绝缘层。 形成在半导体基板的整个表面上的第三绝缘层被干蚀刻以在栅电极的侧壁上形成绝缘层间隔物。 通过沉积工艺在半导体衬底和栅电极的结构上形成第四绝缘层。 也就是说，在栅电极的侧壁上形成绝缘层间隔物之后，通过沉积工艺形成氧化物层以补偿损伤。

    METHOD FOR CONTROLLING SELF-ASSEMBLED SRUCTURE OF POLY(3-HEXYLTHIOPHENE)-BASED BLOCK COPOLYMER
    6.
    发明申请
    METHOD FOR CONTROLLING SELF-ASSEMBLED SRUCTURE OF POLY(3-HEXYLTHIOPHENE)-BASED BLOCK COPOLYMER 审中-公开
    用于控制聚（3-十二烷基） - 嵌段共聚物自组装结构的方法

    公开(公告)号：US20110094587A1

    公开(公告)日：2011-04-28

    申请号：US12707392

    申请日：2010-02-17

    申请人： Kyung Youl BAEK ,  Hoichang Yang ,  Seung Sang Hwang ,  Yeon Hee Choi ,  Yun-Jae Lee ,  Dong Yeop Oh ,  Han Sup Lee

    发明人： Kyung Youl BAEK ,  Hoichang Yang ,  Seung Sang Hwang ,  Yeon Hee Choi ,  Yun-Jae Lee ,  Dong Yeop Oh ,  Han Sup Lee

    IPC分类号： H01L31/0256 ,  H01L51/40 ,  H01L51/30

    CPC分类号： H01L51/0043 ,  G03F7/0002 ,  H01L51/0036 ,  H01L51/0541 ,  H01L51/0545 ,  Y02E10/549

    摘要： Provided is a method for controlling a self-assembled structure of a poly(3-hexylthiophene)-based block copolymer, including: providing a polymer composition containing a block copolymer having a π-conjugated poly(3-hexylthiophene) polymer and a non-conjugated polymer introduced thereto, and a solvent; and coating the polymer composition onto a substrate.According to the method disclosed herein, it is possible to control a self-assembled structure of a poly(3-hexylthiophene)-based block copolymer merely by a relatively simple process including coating the poly(3-hexylthiophene)-based block copolymer onto a substrate with a selected solvent. In this manner, it is possible to control the alignment of conductive domains in the block copolymer so that it is suitable for various organic electronic devices. In addition, the self-assembled polymer structure having various self-assembled structures controlled selectively by the method may be applied to organic electronic devices for designing and developing high-quality devices.

    摘要翻译： 提供一种用于控制聚（3-己基噻吩）基嵌段共聚物的自组装结构的方法，包括：提供含有具有共轭聚（3-己基噻吩）聚合物的嵌段共聚物和非共轭 引入其中的共轭聚合物和溶剂; 并将聚合物组合物涂覆到基底上。 根据本文公开的方法，仅通过相对简单的方法可以控制聚（3-己基噻吩）基嵌段共聚物的自组装结构，包括将聚（3-己基噻吩）基嵌段共聚物涂覆在 底物与选定的溶剂。 以这种方式，可以控制嵌段共聚物中的导电畴的取向，使其适用于各种有机电子器件。 此外，通过该方法选择性地控制的具有各种自组装结构的自组装聚合物结构可以应用于用于设计和开发高质量器件的有机电子器件。

    Method of processing a defect source at a wafer edge region in a semiconductor manufacturing
    9.
    发明授权
    Method of processing a defect source at a wafer edge region in a semiconductor manufacturing 失效
    在半导体制造中在晶片边缘区域处理缺陷源的方法

    公开(公告)号：US06607983B1

    公开(公告)日：2003-08-19

    申请号：US09707353

    申请日：2000-11-06

    申请人： Kwang-Youl Chun ,  Yun-Jae Lee ,  Won-Seong Lee ,  Jeong-Hoon Oh ,  Kyu-Hyun Lee

    发明人： Kwang-Youl Chun ,  Yun-Jae Lee ,  Won-Seong Lee ,  Jeong-Hoon Oh ,  Kyu-Hyun Lee

    IPC分类号： H01L21461

    CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76838 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

    摘要： The present invention provides a method of eliminating or covering a defect source in a wafer edge region for semiconductor fabrication. During the etching process of a sacrificial oxide layer for storage node openings, the sacrificial oxide layer has a rumple topology in the wafer edge region due to etching non-uniformity of a photoresist layer formed on the sacrificial oxide layer. Subsequent deposition of a conductive layer and planarization etching, the conductive layer undesirably remains at the wafer edge region as a defect source. Such conductive contaminant particles dislodge, causing many problems in the wafer main region. The present invention removes such a defect source via two methods. One is to directly remove the defect source using a photoresist pattern exposing thereof. The other is to fix the defect source in place in the wafer edge region by protecting thereof by a photoresist pattern during subsequent cleaning processes.

    摘要翻译： 本发明提供一种消除或覆盖用于半导体制造的晶片边缘区域中的缺陷源的方法。 在用于存储节点开口的牺牲氧化物层的蚀刻工艺期间，由于蚀刻在牺牲氧化物层上形成的光致抗蚀剂层的不均匀性，牺牲氧化物层在晶片边缘区域中具有隆起的拓扑结构。 随后沉积导电层和平坦化蚀刻，导电层不期望地保留在晶片边缘区域作为缺陷源。 这种导电性污染物颗粒移动，在晶片主区域引起许多问题。 本发明通过两种方法去除这种缺陷源。 一个是使用其曝光的光致抗蚀剂图案直接去除缺陷源。 另一种是通过在随后的清洁过程中通过光致抗蚀剂图案的保护来将缺陷源固定在晶片边缘区域中。