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    Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing region
    1.
    发明授权
    Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing region 有权
    绝缘体上半导体基板和结构包括多阶射频谐波抑制区域

    公开(公告)号：US08299537B2

    公开(公告)日：2012-10-30

    申请号：US12369099

    申请日：2009-02-11

    申请人： Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

    发明人： Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

    IPC分类号： H01L21/70

    CPC分类号： H01L21/7624 ,  H01L21/26506 ,  H01L21/84 ,  H01L27/1203

    摘要： A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure.

    摘要翻译： 绝缘体上半导体衬底和相关半导体结构以及绝缘体上半导体衬底和相关半导体结构的制造方法提供了一种位于并形成在基底半导体内的多阶射频谐波抑制区域 在绝缘体上半导体衬底内的掩埋介质层与基底半导体衬底的界面下方的位置处的衬底。 多级射频谐波抑制区域可以包括离子注入原子，例如但不限于稀有气体原子，以在对射频设备供电时提供抑制的多阶射频谐波，例如但不限于无线电 位于和形成在半导体结构内的表面半导体层内和之上的高频互补金属氧化物半导体器件（或替代地，无源器件）。

    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE
    3.
    发明申请
    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE 有权
    用于减少谐波的硅绝缘体（SOI）结构和形成结构的方法

    公开(公告)号：US20110127529A1

    公开(公告)日：2011-06-02

    申请号：US12627343

    申请日：2009-11-30

    申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

    发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

    IPC分类号： H01L27/12 ,  H01L21/762

    CPC分类号： H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

    摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

    摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。

    SYSTEM AND METHOD FOR DETECTING LOCAL MECHANICAL STRESS IN INTEGREATED DEVICES
    5.
    发明申请
    SYSTEM AND METHOD FOR DETECTING LOCAL MECHANICAL STRESS IN INTEGREATED DEVICES 有权
    用于检测集成设备中的局部机械应力的系统和方法

    公开(公告)号：US20090219508A1

    公开(公告)日：2009-09-03

    申请号：US12039830

    申请日：2008-02-29

    申请人： Lloyd Bumm ,  Daminda Dahayanaka ,  Philip V. Kaszuba ,  Leon Moszkowicz ,  James A. Slinkman

    发明人： Lloyd Bumm ,  Daminda Dahayanaka ,  Philip V. Kaszuba ,  Leon Moszkowicz ,  James A. Slinkman

    IPC分类号： G01B11/16

    CPC分类号： G01B21/32 ,  G01Q60/30

    摘要： A method of detecting local mechanical stress in integrated devices is provided, the method comprising: enabling the detection of a photovoltage difference between a scan probe device and a surface portion of an integrated device, the scan probe device being configured to deflect in response to the photovoltage difference; measuring the deflection of the scan probe device in response to the photovoltage difference between the scan probe device and the surface portion of the integrated device; and calculating a local stress level within the integrated device by determining a local work function of the surface portion of the integrated device based upon the deflection of the scan probe device.

    摘要翻译： 提供了一种在集成器件中检测局部机械应力的方法，所述方法包括：使得能够检测扫描探针器件与集成器件的表面部分之间的光电压差，扫描探针器件被配置为响应于 光电压差; 测量所述扫描探针装置响应于所述扫描探针装置与所述集成装置的所述表面部分之间的光电压差的偏转; 以及通过基于所述扫描探针装置的偏转来确定所述集成装置的所述表面部分的局部功函数来计算所述集成装置内的局部应力水平。

    HIGH RESISTIVITY SOI BASE WAFER USING THERMALLY ANNEALED SUBSTRATE
    6.
    发明申请
    HIGH RESISTIVITY SOI BASE WAFER USING THERMALLY ANNEALED SUBSTRATE 有权
    使用热退火衬底的高电阻SOI衬底波形

    公开(公告)号：US20090110898A1

    公开(公告)日：2009-04-30

    申请号：US11931371

    申请日：2007-10-31

    申请人： Max Levy ,  Dale Martin ,  Gerd Pfeiffer ,  James A. Slinkman

    发明人： Max Levy ,  Dale Martin ,  Gerd Pfeiffer ,  James A. Slinkman

    IPC分类号： H01L21/30 ,  B32B7/02 ,  B32B9/00 ,  B32B9/04

    CPC分类号： H01L21/76254 ,  H01L21/76256 ,  H01L29/78603 ,  Y10T428/249921 ,  Y10T428/31504

    摘要： A method of forming a semiconductor-on-insulator (SOI) substrate using a thermal annealing process to provide a semiconductor base wafer having a thin high resistivity surface layer that is positioned at the interface with the buried insulating layer is provided. Specifically, the inventive method fabricates an a semiconductor-on-insulator (SOI) substrate having an SOI layer and a semiconductor base wafer that are separated, at least in part, by a buried insulating layer, wherein the semiconductor base wafer includes a high resistivity (HR) surface layer located on a lower resistivity semiconductor portion of the semiconductor base wafer, and the HR surface layer forms an interface with the buried insulating layer.

    摘要翻译： 提供一种使用热退火工艺形成绝缘体上半导体（SOI）衬底的方法，以提供具有位于与掩埋绝缘层的界面处的薄的高电阻率表面层的半导体基底晶片。 具体地，本发明的方法制造具有至少部分由掩埋绝缘层分离的SOI层和半导体基底晶片的绝缘体上半导体（SOI）衬底，其中半导体基底晶片包括高电阻率 （HR）表层，并且所述HR表面层与所述掩埋绝缘层形成界面。

    STI stress modification by nitrogen plasma treatment for improving performance in small width devices
    8.
    发明授权
    STI stress modification by nitrogen plasma treatment for improving performance in small width devices 失效
    通过氮等离子体处理进行STI应力改进，以改善小宽度器件的性能

    公开(公告)号：US06887798B2

    公开(公告)日：2005-05-03

    申请号：US10250047

    申请日：2003-05-30

    申请人： Sadanand V. Deshpande ,  Bruce B. Doris ,  Werner A. Rausch ,  James A. Slinkman

    发明人： Sadanand V. Deshpande ,  Bruce B. Doris ,  Werner A. Rausch ,  James A. Slinkman

    IPC分类号： H01L21/318 ,  H01L21/762 ,  H01L29/10 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L29/7842 ,  H01L21/3185 ,  H01L21/76237 ,  H01L29/1033

    摘要： A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.

    摘要翻译： 一种通过氮等离子体处理调节小宽度装置的鸟嘴形成引起的应力的方法。 氮等离子体工艺形成围绕沟槽壁的氮化物衬垫，其用于在随后的氧化步骤期间防止在隔离区中形成鸟嘴。 在一个实施例中，等离子体氮化处理发生在沟槽蚀刻之后，但在沟槽填充之前。 在另一个实施例中，等离子体氮化处理发生在沟槽填充之后。 在另一个实施例中，在等离子体氮化处理之前，在蚀刻的衬底的预定有效区域上形成块掩模。 该实施例用于保护PFET器件区域免受等离子体氮化处理，从而提供形成PFET器件区域的装置，其中由鸟嘴形成引起的应力增加了PFET的器件性能。