公开(公告)号：US07585614B2

公开(公告)日：2009-09-08

申请号：US10711458

申请日：2004-09-20

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit ,  James A. Slinkman

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit ,  James A. Slinkman

IPC分类号： G03F7/00

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： A method of patterning which provides images substantially smaller than that possible by lithographic techniques is provided. In the method of the invention, a substrate has a memory layer and a sacrificial layer formed thereon. An image is patterned onto the memory layer by protecting an edge during an etching step using chemical oxide removal (COR) processes, for example. Another edge is memorized in the layer. The sacrificial layer is removed to expose another memorized edge, which is used to define a pattern in an underlying layer.

摘要翻译： 提供了一种通过光刻技术提供显着小于可能的图像的图案化方法。 在本发明的方法中，衬底具有形成在其上的存储层和牺牲层。 例如，通过使用化学氧化物去除（COR）工艺在蚀刻步骤期间保护边缘，将图像图案化到存储层上。 另一个边缘被记住在图层中。 去除牺牲层以露出另一个存储的边缘，其用于在下层中定义图案。

公开(公告)号：US06875685B1

公开(公告)日：2005-04-05

申请号：US10605766

申请日：2003-10-24

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit ,  James A. Slinkman

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit ,  James A. Slinkman

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a gas dielectric with support structure on a semiconductor device structure provides low capacitance and adequate support for a conductor of the semiconductor device structure. A conductive structure, such as via or interconnect, is formed in a wing-layer dielectric. A support is then formed that connects to the conductive structure, the support including an area thereunder. The wiring-layer dielectric is then removed from the area to form a gas dielectric.

摘要翻译： 在半导体器件结构上形成具有支撑结构的气体电介质的方法为半导体器件结构的导体提供低电容和足够的支撑。 在翼层电介质中形成诸如通孔或互连的导电结构。 然后形成连接到导电结构的支撑件，支撑件包括其下的区域。 然后从该区域去除布线层电介质以形成气体电介质。

公开(公告)号：US07089138B1

公开(公告)日：2006-08-08

申请号：US10906590

申请日：2005-02-25

申请人： Pierre J. Bouchard ,  Mark C. Hakey ,  Mark E. Masters ,  Leah M. P. Pastel ,  James A. Slinkman ,  David P. Vallett

发明人： Pierre J. Bouchard ,  Mark C. Hakey ,  Mark E. Masters ,  Leah M. P. Pastel ,  James A. Slinkman ,  David P. Vallett

IPC分类号： G06F11/00

CPC分类号： G01R31/2856 ,  G01R31/2831 ,  G01R31/318511 ,  G01R31/3187

摘要： A diagnostic system and method for testing an integrated circuit during fabrication thereof. The diagnostic system has at least one integrated circuit chip that has an electrical signature associated with it; a sacrificial circuit that is adjacent to the integrated circuit chip and has a known electrical signature associated with it and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit indicates that the integrated circuit chip is mis-designed. The diagnostic system further includes a semiconductor wafer that has a plurality of integrated circuit chips and a kerf area separating one integrated circuit chip from another integrated circuit chip. A mis-designed integrated circuit chip has abnormally functioning circuitry.

摘要翻译： 一种在其制造期间测试集成电路的诊断系统和方法。 诊断系统具有至少一个具有与其相关联的电特征的集成电路芯片; 牺牲电路，其与集成电路芯片相邻并且具有与其相关联的已知电气签名和故意错误设计的电路; 以及比较器，用于将集成电路芯片的电特征与牺牲电路的已知电特征进行比较，其中集成电路芯片的电特征中与牺牲电路的已知电气签名的匹配指示集成电路 芯片设计错误。 诊断系统还包括具有多个集成电路芯片的半导体晶片和将一个集成电路芯片与另一个集成电路芯片分离的切口区域。 错误设计的集成电路芯片具有异常功能的电路。

公开(公告)号：US06417515B1

公开(公告)日：2002-07-09

申请号：US09527192

申请日：2000-03-17

申请人： Howard T. Barrett ,  John J. Ellis-Monaghan ,  Toshiharu Furukawa ,  James A. Slinkman

发明人： Howard T. Barrett ,  John J. Ellis-Monaghan ,  Toshiharu Furukawa ,  James A. Slinkman

IPC分类号： H01J37317

CPC分类号： H01J37/3171 ,  H01J2237/30466 ,  H01J2237/31703

摘要： A substrate, such as a semiconductor chip or wafer, is implanted along with product wafers in an ion implant vacuum system. The substrate is then annealed in an annealing step that is accomplished while the substrate is within the vacuum system. The annealer is a rapid thermal annealer, such as a laser annealer or a flash lamp annealer. The annealing step does not affect the product wafers. Then a measurement is performed on the implanted and annealed substrate while it is within the vacuum system that can be suitably correlated with implant dose. The measurement can be with a technique such as a four point probe or with a tool that measures optical reflectivity from a surface of the implanted substrate. An additional implant can then be provided to product wafers if necessary to come closer to the desired dose.

摘要翻译： 将衬底（例如半导体芯片或晶片）与产品晶片一起植入离子注入真空系统中。 然后在基板处于真空系统内的退火步骤中退火基板。 退火炉是快速热退火炉，例如激光退火炉或闪光灯退火炉。 退火步骤不影响产品晶圆。 然后对植入和退火的基底进行测量，同时它在可以适当地与植入剂量相关联的真空系统内。 该测量可以采用诸如四点探针的技术或者用来测量从植入的衬底的表面的光学反射率的工具。 如果需要，可以将另外的植入物提供给产品晶片以更接近所需剂量。

公开(公告)号：US06274465B1

公开(公告)日：2001-08-14

申请号：US09538309

申请日：2000-03-30

申请人： Arne W. Ballantine ,  John J. Ellis-Monaghan ,  Toshiharu Furukawa ,  Glenn R. Miller ,  James A. Slinkman

发明人： Arne W. Ballantine ,  John J. Ellis-Monaghan ,  Toshiharu Furukawa ,  Glenn R. Miller ,  James A. Slinkman

IPC分类号： H01L2104

CPC分类号： H01L21/324 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/326

摘要： A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to a DC electric field.

摘要翻译： 一种用于在半导体器件中形成期望的接合剖面的方法。 将至少一种掺杂剂引入到半导体衬底中。 所述至少一种掺杂剂通过半导体衬底和所述至少一种掺杂剂退火而在半导体衬底中扩散，同时将半导体衬底暴露于DC电场。

公开(公告)号：US08299537B2

公开(公告)日：2012-10-30

申请号：US12369099

申请日：2009-02-11

申请人： Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

发明人： Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： H01L21/70

CPC分类号： H01L21/7624 ,  H01L21/26506 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure.

摘要翻译： 绝缘体上半导体衬底和相关半导体结构以及绝缘体上半导体衬底和相关半导体结构的制造方法提供了一种位于并形成在基底半导体内的多阶射频谐波抑制区域 在绝缘体上半导体衬底内的掩埋介质层与基底半导体衬底的界面下方的位置处的衬底。 多级射频谐波抑制区域可以包括离子注入原子，例如但不限于稀有气体原子，以在对射频设备供电时提供抑制的多阶射频谐波，例如但不限于无线电 位于和形成在半导体结构内的表面半导体层内和之上的高频互补金属氧化物半导体器件（或替代地，无源器件）。

公开(公告)号：US20120168817A1

公开(公告)日：2012-07-05

申请号：US13238414

申请日：2011-09-21

申请人： Michel J. Abou-Khalil ,  Alan B. Botula ,  Alvin J. Joseph ,  Theodore J. Letavic ,  James A. Slinkman

发明人： Michel J. Abou-Khalil ,  Alan B. Botula ,  Alvin J. Joseph ,  Theodore J. Letavic ,  James A. Slinkman

IPC分类号： H01L27/088 ,  H01L21/76 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66681 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66704 ,  H01L29/66795 ,  H01L29/7436 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/785

摘要： Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage. Discrete conductive field (CF) plates are adjacent to opposing sides of the drain drift region, each having an angled sidewall such that the area between the drain drift region and the CF plate has a continuously increasing width along the length of the drain drift region from the channel region to the drain region. The CF plates can comprise polysilicon or metal structures or dopant implant regions within the same semiconductor body as the drain drift region. The areas between the CF plates and the drain drift region can comprise tapered dielectric regions or, alternatively, tapered depletion regions within the same semiconductor body as the drain drift region. Also disclosed are embodiments of a method for forming an LEDMOSFET and embodiments of a silicon-controlled rectifier (SCR) incorporating such LEDMOSFETs.

摘要翻译： 公开了具有高漏极对体击穿电压的横向延伸漏极，金属氧化物半导体，场效应晶体管（LEDMOSFET）的实施例。 离散导电场（CF）板与漏极漂移区的相对侧相邻，每侧具有成角度的侧壁，使得漏极漂移区和CF板之间的区域沿着漏极漂移区的长度具有连续增加的宽度， 沟道区到漏极区。 CF板可以包括与漏极漂移区相同的半导体主体内的多晶硅或金属结构或掺杂剂注入区。 CF板和漏极漂移区域之间的区域可以包括与漏极漂移区域相同的半导体本体内的锥形介质区域或者替代地，锥形耗尽区域。 还公开了用于形成LEDMOSFET的方法的实施例和结合了这种LEDMOSFET的可控硅整流器（SCR）的实施例。

公开(公告)号：US20110127529A1

公开(公告)日：2011-06-02

申请号：US12627343

申请日：2009-11-30

申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： H01L27/12 ,  H01L21/762

CPC分类号： H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。

公开(公告)号：US20090219508A1

公开(公告)日：2009-09-03

申请号：US12039830

申请日：2008-02-29

申请人： Lloyd Bumm ,  Daminda Dahayanaka ,  Philip V. Kaszuba ,  Leon Moszkowicz ,  James A. Slinkman

发明人： Lloyd Bumm ,  Daminda Dahayanaka ,  Philip V. Kaszuba ,  Leon Moszkowicz ,  James A. Slinkman

IPC分类号： G01B11/16

CPC分类号： G01B21/32 ,  G01Q60/30

摘要： A method of detecting local mechanical stress in integrated devices is provided, the method comprising: enabling the detection of a photovoltage difference between a scan probe device and a surface portion of an integrated device, the scan probe device being configured to deflect in response to the photovoltage difference; measuring the deflection of the scan probe device in response to the photovoltage difference between the scan probe device and the surface portion of the integrated device; and calculating a local stress level within the integrated device by determining a local work function of the surface portion of the integrated device based upon the deflection of the scan probe device.

摘要翻译： 提供了一种在集成器件中检测局部机械应力的方法，所述方法包括：使得能够检测扫描探针器件与集成器件的表面部分之间的光电压差，扫描探针器件被配置为响应于 光电压差; 测量所述扫描探针装置响应于所述扫描探针装置与所述集成装置的所述表面部分之间的光电压差的偏转; 以及通过基于所述扫描探针装置的偏转来确定所述集成装置的所述表面部分的局部功函数来计算所述集成装置内的局部应力水平。

公开(公告)号：US20090110898A1

公开(公告)日：2009-04-30

申请号：US11931371

申请日：2007-10-31

申请人： Max Levy ,  Dale Martin ,  Gerd Pfeiffer ,  James A. Slinkman

发明人： Max Levy ,  Dale Martin ,  Gerd Pfeiffer ,  James A. Slinkman

IPC分类号： H01L21/30 ,  B32B7/02 ,  B32B9/00 ,  B32B9/04

CPC分类号： H01L21/76254 ,  H01L21/76256 ,  H01L29/78603 ,  Y10T428/249921 ,  Y10T428/31504

摘要： A method of forming a semiconductor-on-insulator (SOI) substrate using a thermal annealing process to provide a semiconductor base wafer having a thin high resistivity surface layer that is positioned at the interface with the buried insulating layer is provided. Specifically, the inventive method fabricates an a semiconductor-on-insulator (SOI) substrate having an SOI layer and a semiconductor base wafer that are separated, at least in part, by a buried insulating layer, wherein the semiconductor base wafer includes a high resistivity (HR) surface layer located on a lower resistivity semiconductor portion of the semiconductor base wafer, and the HR surface layer forms an interface with the buried insulating layer.

摘要翻译： 提供一种使用热退火工艺形成绝缘体上半导体（SOI）衬底的方法，以提供具有位于与掩埋绝缘层的界面处的薄的高电阻率表面层的半导体基底晶片。 具体地，本发明的方法制造具有至少部分由掩埋绝缘层分离的SOI层和半导体基底晶片的绝缘体上半导体（SOI）衬底，其中半导体基底晶片包括高电阻率 （HR）表层，并且所述HR表面层与所述掩埋绝缘层形成界面。