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    Semiconductor device with an ion implanted stabilization layer
    1.
    发明授权
    Semiconductor device with an ion implanted stabilization layer 失效
    具有离子注入稳定层的半导体器件

    公开(公告)号：US4496963A

    公开(公告)日：1985-01-29

    申请号：US19135

    申请日：1979-03-09

    申请人： James L. Dunkley ,  Robert C. Dobkin

    发明人： James L. Dunkley ,  Robert C. Dobkin

    IPC分类号： H01L29/10 ,  H01L29/808 ,  H01L29/80

    CPC分类号： H01L29/808 ,  H01L29/1029

    摘要： A semiconductor device wherein surface stabilization is provided by a shallow layer of ion implanted doping material on the surface of the semiconductor and beneath the passivating oxide layer. One embodiment is a bipolar transistor including a collector region, a base region and an emitter region, the base region being provided with the shallow ion implanted layer at the surface thereof. Another embodiment is a zener diode device with an anode region and a cathode region, the cathode region being provided with the shallow ion implanted layer at the surface thereof. Another embodiment is a JFET with a gate region and a source and drain region and a channel region extending through the gate region between the source and drain regions, the channel region being provided with the shallow ion implanted layer at the surface thereof.

    摘要翻译： 一种半导体器件，其中表面稳定性由半导体表面上的钝化氧化物层下方的离子注入掺杂材料的浅层提供。 一个实施例是包括集电极区域，基极区域和发射极区域的双极晶体管，所述基极区域在其表面设置有浅离子注入层。 另一个实施例是具有阳极区域和阴极区域的齐纳二极管器件，阴极区域在其表面设有浅离子注入层。 另一实施例是具有栅极区域和源极和漏极区域以及延伸穿过源极和漏极区域之间的栅极区域的沟道区域的JFET，沟道区域在其表面处设置有浅离子注入层。

    Process for manufacturing a JFET with an ion implanted stabilization layer
    2.
    发明授权
    Process for manufacturing a JFET with an ion implanted stabilization layer 失效
    用离子注入稳定层制造JFET的工艺

    公开(公告)号：US4393575A

    公开(公告)日：1983-07-19

    申请号：US284664

    申请日：1981-07-20

    申请人： James L. Dunkley ,  Robert C. Dobkin

    发明人： James L. Dunkley ,  Robert C. Dobkin

    IPC分类号： H01L29/10 ,  H01L29/808 ,  H01L21/265

    CPC分类号： H01L29/1058 ,  H01L29/808

    摘要： A semiconductor device wherein surface stabilization is provided by a shallow layer of ion implanted doping material on the surface of the semiconductor and beneath the passivating oxide layer. One embodiment is a bipolar transistor including a collector region, a base region and an emitter region, the base region being provided with the shallow ion implanted layer at the surface thereof. Another embodiment is a zener diode device with an anode region and a cathode region, the cathode region being provided with the shallow ion implanted layer at the surface thereof. Another embodiment is a JFET with a gate region and a source and drain region and a channel region extending through the gate region between the source and drain regions, the channel region being provided with the shallow ion implanted layer at the surface thereof.

    摘要翻译： 一种半导体器件，其中表面稳定性由半导体表面上的钝化氧化物层下方的离子注入掺杂材料的浅层提供。 一个实施例是包括集电极区域，基极区域和发射极区域的双极晶体管，所述基极区域在其表面设置有浅离子注入层。 另一个实施例是具有阳极区域和阴极区域的齐纳二极管器件，阴极区域在其表面设有浅离子注入层。 另一实施例是具有栅极区域和源极和漏极区域以及延伸穿过源极和漏极区域之间的栅极区域的沟道区域的JFET，沟道区域在其表面处设置有浅离子注入层。

    METHOD FOR CLAMPING A SEMICONDUCTOR REGION AT OR NEAR GROUND
    3.
    发明申请
    METHOD FOR CLAMPING A SEMICONDUCTOR REGION AT OR NEAR GROUND 审中-公开
    用于夹紧或接近半导体区域的方法

    公开(公告)号：US20090121770A1

    公开(公告)日：2009-05-14

    申请号：US12033600

    申请日：2008-02-19

    申请人： Samuel Patrick Rankin ,  Robert C. Dobkin

    发明人： Samuel Patrick Rankin ,  Robert C. Dobkin

    IPC分类号： H03K5/08

    CPC分类号： G05F3/265 ,  H01L27/0248

    摘要： A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio.

    摘要翻译： 钳位电路钳位由n型半导体区域接收的电压，而不使用肖特基晶体管。 钳位电路包括电流镜以及第一和第二双极晶体管。 电流镜接收第一电流并提供响应的第二电流。 第一电流由第一双极晶体管接收，第二电流由第二双极晶体管接收。 第一和第二双极晶体管的基极 - 发射极结电压之间的差异部分地限定了n型区域被钳位的电压。 为了正确启动电路，从设置在电流反射镜中的晶体管的基极/栅极端子取出电流。 该电路可选地包括一对交叉耦合的晶体管，以减少输出阻抗并提高电源抑制比。

    Methods and circuits for frequency modulation that reduce the spectral noise of switching regulators
    4.
    发明授权
    Methods and circuits for frequency modulation that reduce the spectral noise of switching regulators 有权
    用于频率调制的方法和电路，可降低开关稳压器的频谱噪声

    公开(公告)号：US07362191B2

    公开(公告)日：2008-04-22

    申请号：US10835693

    申请日：2004-04-29

    申请人： Yuhui Chen ,  Doug LaPorte ,  Randy Guy Flatness ,  Robert C. Dobkin

    发明人： Yuhui Chen ,  Doug LaPorte ,  Randy Guy Flatness ,  Robert C. Dobkin

    IPC分类号： H03B29/00 ,  H02M7/00

    CPC分类号： H04B15/04 ,  H02M1/44 ,  H02M3/156 ,  H04B2215/067 ,  H04B2215/069

    摘要： The present invention comprises methods and circuits for spread spectrum frequency modulation that reduce peak spectral noise at the outputs or inputs of switching regulators. More specifically, the present invention modulates the operating frequency of the switching regulator in accordance with a frequency modulation waveform having a shape coordinated to a peak noise amplitude waveform that describes the correlation between the operating frequency of a switching regulator and the peak noise amplitude at the regulator's input or output absent spread spectrum frequency modulation.

    摘要翻译： 本发明包括用于扩展频谱调制的方法和电路，其减少开关调节器的输出或输入处的峰值频谱噪声。 更具体地，本发明根据具有与峰值噪声幅度波形协调的形状的频率调制波形来调制开关调节器的工作频率，该峰值噪声幅度波形描述了开关调节器的工作频率与峰值噪声振幅之间的相关性 调节器的输入或输出没有扩频调频。

    Bidirectional power conversion with multiple control loops
    5.
    发明授权
    Bidirectional power conversion with multiple control loops 有权
    具有多个控制回路的双向功率转换

    公开(公告)号：US06894461B1

    公开(公告)日：2005-05-17

    申请号：US10270799

    申请日：2002-10-11

    申请人： Thomas P. Hack ,  Robert C. Dobkin

    发明人： Thomas P. Hack ,  Robert C. Dobkin

    IPC分类号： G05F1/70 ,  H02K7/02 ,  H02M3/158 ,  H02M3/335 ,  H02M5/42

    CPC分类号： H02M3/33584 ,  G05F1/70 ,  H02M3/1582 ,  Y10T307/707

    摘要： Bidirectional power conversion systems provide the ability to change power attributes to and from a component. Current bidirectional power conversion systems use a unidirectional power converter for each direction. The integration of the two normally independent power converters results in a bidirectional power converter with nearly half the size, weight, volume, cost and complexity. Described are embodiments of bidirectional power conversion systems that allow power transfer between two or more components without requiring the use of separate unidirectional power converters.

    摘要翻译： 双向功率转换系统提供了向组件更改功率属性的能力。 目前的双向功率转换系统为每个方向使用单向功率转换器。 两个正常独立的功率转换器的集成导致双向功率转换器具有将近一半的尺寸，重量，体积，成本和复杂性。 描述了允许在两个或更多个组件之间进行功率传输而不需要使用单独的单向功率转换器的双向功率转换系统的实施例。

    Error signal generation circuit for low dropout regulators
    7.
    发明授权
    Error signal generation circuit for low dropout regulators 失效
    用于低压差稳压器的误差信号发生电路

    公开(公告)号：US5485109A

    公开(公告)日：1996-01-16

    申请号：US241505

    申请日：1994-05-12

    申请人： Robert C. Dobkin ,  Carl T. Nelson ,  Dennis P. O'Neill

    发明人： Robert C. Dobkin ,  Carl T. Nelson ,  Dennis P. O'Neill

    IPC分类号： G05F1/56 ,  G05F1/573 ,  H03K5/153

    CPC分类号： G05F1/573 ,  G05F1/56

    摘要： A three terminal control circuit for a low dropout voltage regulator having a PNP pass transistor is provided. The control circuit is capable of pulling the base-drive point down to a voltage of 3.0 volts or less to permit a current limiting resistor to be inserted between the base drive point and the base of the PNP pass transistor. The control circuit includes a pair of small-valued capacitors for providing stable operation with different output capacitors. The control circuit can also be used with p-channel FET pass transistors.

    摘要翻译： 提供一种具有PNP传输晶体管的低压差稳压器的三端控制电路。 控制电路能够将基极驱动点拉低至3.0伏或更小的电压，以允许限流电阻器插入在PNP传输晶体管的基极驱动点和基极之间。 该控制电路包括一对小值电容器，用于提供与不同输出电容器的稳定操作。 控制电路也可以与p沟道FET传输晶体管一起使用。

    Electrostatic discharge clamp using vertical NPN transistor
    8.
    发明授权
    Electrostatic discharge clamp using vertical NPN transistor 失效
    使用垂直NPN晶体管的静电放电钳

    公开(公告)号：US5212618A

    公开(公告)日：1993-05-18

    申请号：US518151

    申请日：1990-05-03

    申请人： Dennis P. O'Neill ,  William C. Rempfer ,  Robert C. Dobkin

    发明人： Dennis P. O'Neill ,  William C. Rempfer ,  Robert C. Dobkin

    IPC分类号： H01L27/02

    CPC分类号： H01L27/0248

    摘要： An electrostatic discharge protection clamp particularly useful for with bipolar and biCMOS integrated circuits include an NPN transistor formed in an isolated tub in an epitaxial layer grown on a substrate. The collector of the NPN transistor is connected to the input terminal, and the emitter of the NPN transistor is connected to the substrate. A resistor interconnects the base and the emitter. Advantageously, the P-doped base can abut the P-doped isolation region forming the tub, and the P-doped isolation region can interconnect the emitter to the substrate. Below BV.sub.CES the clamp will look like an open circuit, and above BV.sub.CES the transistor will start conducting current. The transistor will break down collector to base. Conduction of the transistor causes a voltage drop across the base-emitter junction, and when this voltage drop exceeds the base-emitter forward voltage the transistor will turn on. Once the transistor is turned on and current starts flowing in the emitter, avalanche effects will cause the breakdown voltage to snap back to BV.sub.CEO and remain there until the emitter current drops below some low level, which will be at the end of the electrostatic discharge pulse. In the negative direction the tub to substrate diode provides an effective clamp which will clamp the voltage to a low value and limit the power dissipation in the junction. Alternatively, a bidirectional clamp can be provided in which a second NPN transistor is fabricated in the tub with the emitter of the second transistor connected to the input terminal and the collectors of the two transistors being interconnected by the N-doped epitaxial layer of the tub. The dopant conductivities can be reversed.

    摘要翻译： 特别适用于双极和biCMOS集成电路的静电放电保护钳包括形成在衬底上生长的外延层中的隔离桶中的NPN晶体管。 NPN晶体管的集电极连接到输入端子，NPN晶体管的发射极连接到基板。 电阻器将基极和发射极互连。 有利地，P掺杂的基极可以邻接形成桶的P掺杂隔离区，并且P掺杂隔离区可以将发射极与衬底互连。 在BVCES下方，钳位将看起来像一个开路，而在BVCES之上，晶体管将开始导通电流。 晶体管会将集电极分解为基极。 晶体管的导通导致基极 - 发射极结两端的电压降，当该电压降超过基极 - 发射极正向电压时，晶体管将导通。 一旦晶体管导通并且电流开始在发射极中流动，雪崩效应将导致击穿电压反弹至BVCEO，并保持在那里，直到发射极电流下降到一些低电平，这将在静电放电脉冲结束时 。 在负向方向上，桶至衬底二极管提供有效钳位，其将电压钳位到低值并限制结中的功率耗散。 或者，可以提供双向钳位，其中第二NPN晶体管制造在桶中，其中第二晶体管的发射极连接到输入端，并且两个晶体管的集电极通过盆的N掺杂外延层互连 。 掺杂剂的电导率可以颠倒。

    Non-linear temperature generator circuit
    10.
    发明授权
    Non-linear temperature generator circuit 失效
    非线性温度发生器电路

    公开(公告)号：US4843302A

    公开(公告)日：1989-06-27

    申请号：US189479

    申请日：1988-05-02

    申请人： Robert C. Dobkin ,  Carl T. Nelson

    发明人： Robert C. Dobkin ,  Carl T. Nelson

    IPC分类号： G05F3/30

    CPC分类号： G05F3/30 ,  Y10S323/907

    摘要： A non-linear temperature correction circuit is provided which utilizes, in one embodiment, a pair of semiconductor elements such as a pair of transistors electrically connected to a common biasing current having a negative temperature coefficient and a negative temperature coefficient voltage is applied between the bases of the transistors. The output of one of the transistors is a non-linear output current which is non-linear with respect to temperature and where the output current has an inflection point.

    摘要翻译： 提供一种非线性温度校正电路，其在一个实施例中利用一对半导体元件，例如一对晶体管，其电连接到具有负温度系数和负温度系数电压的公共偏置电流，在基极 的晶体管。 一个晶体管的输出是非线性输出电流，其相对于温度是非线性的，并且其中输出电流具有拐点。