公开(公告)号：US20060188417A1

公开(公告)日：2006-08-24

申请号：US11063813

申请日：2005-02-23

申请人： James Roth ,  Vincent Leung ,  Brian Doerksen ,  Robin McGlynn

发明人： James Roth ,  Vincent Leung ,  Brian Doerksen ,  Robin McGlynn

IPC分类号： B01J10/00

CPC分类号： B01J8/062 ,  B01J6/004 ,  C10G9/20

摘要： System and method are disclosed for increasing the effectiveness of the lower tubes in a delayed coker furnace. The system and method involve arranging the tubes so that the lower tubes are as close to the heat source as the upper tubes. Such an arrangement allows all the tubes to have substantially the same amount of radiant flux. In some implementations, it is also possible to conform the refractory floor to the arrangement of the tubes.

摘要翻译： 公开了用于提高延迟焦化炉中下管的有效性的系统和方法。 该系统和方法包括布置管，使得下管与上管近似于热源。 这种布置允许所有管具有基本相同量的辐射通量。 在一些实施方案中，还可以使耐火地板与管的布置一致。

公开(公告)号：US5801579A

公开(公告)日：1998-09-01

申请号：US808237

申请日：1997-02-28

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Hollmer ,  Shoichi Kawamura ,  Michael Chung ,  Vincent Leung ,  Masaru Yano

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Hollmer ,  Shoichi Kawamura ,  Michael Chung ,  Vincent Leung ,  Masaru Yano

IPC分类号： G11C8/08 ,  G11C16/12 ,  G05F1/10

CPC分类号： G11C16/12 ,  G11C8/08

摘要： Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them. In the preferred embodiment, both the regulation transistors and the discharge transistors are included in the high voltage pass gate.

摘要翻译： 两个NMOS升压晶体管的源极连接到高压输入端，而它们的漏极和栅极交叉连接。 两个耦合电容器将两个交替相位时钟连接到两个交叉连接的升压晶体管的栅极。 NMOS传输晶体管的栅极连接到一个NMOS升压晶体管的漏极，其源极连接到高压输入，其漏极连接到输出。 在一个实施例中，两个二极管连接的调节晶体管将升压晶体管的栅极连接到高电压输入。 这些连接确保升压晶体管的栅极和传输晶体管的栅极不会达到高于高电压输入以上的一个阈值电压的电压。 在另一个实施例中，两个放电晶体管的漏极连接到解码输入，其源极连接到升压晶体管的栅极，并且其栅极连接到正电源。 通过将解码输入设置为零伏特，升压晶体管和传输晶体管的栅极处的电压保持在零伏特，从而禁止它们。 在优选实施例中，调节晶体管和放电晶体管都包括在高压通栅中。

公开(公告)号：US07557617B1

公开(公告)日：2009-07-07

申请号：US11649618

申请日：2007-01-03

申请人： Vincent Leung

发明人： Vincent Leung

IPC分类号： H03K19/094 ,  G11C8/00

CPC分类号： G11C8/10

摘要： A digital decoder is provided that produces true and complementary output signals. The digital decoder may be formed from n-channel and p-channel metal-oxide-semiconductor transistors. The digital decoder produces four true outputs and four complementary outputs from two inputs. A first of the true outputs and a first of the complementary outputs are provided using a NOR gate and an inverter. A NAND gate and an inverter are used to provide a second of the true outputs and a second of the complementary outputs. Third and fourth complementary outputs are produced using first and second logic circuits. The first and second logic circuits are powered using only a positive power supply voltage. Third and fourth true outputs are produced using third and fourth logic circuits. The third and fourth logic circuits are powered using only a ground power supply voltage. The logic circuits each include an n-channel and p-channel transistor pair.

摘要翻译： 提供了产生真实和互补的输出信号的数字解码器。 数字解码器可以由n沟道和p沟道金属氧化物半导体晶体管形成。 数字解码器从两个输入产生四个真实输出和四个互补输出。 使用NOR门和逆变器提供第一个真实输出和第一个互补输出。 NAND门和反相器用于提供第二个真实输出和第二个互补输出。 使用第一和第二逻辑电路产生第三和第四互补输出。 第一和第二逻辑电路仅使用正电源电压供电。 使用第三和第四逻辑电路产生第三和第四真实输出。 第三和第四逻辑电路仅使用接地电源电压供电。 逻辑电路各自包括n沟道和p沟道晶体管对。

公开(公告)号：US20070147040A1

公开(公告)日：2007-06-28

申请号：US11319127

申请日：2005-12-27

申请人： Vincent Leung

发明人： Vincent Leung

IPC分类号： F21V23/02

CPC分类号： F21V7/09 ,  F21L4/00 ,  F21Y2103/30 ,  Y02B20/19

摘要： A reflector/concentrator for a compact fluorescent lamp includes a concave reflector sized to hold a compact fluorescent lamp and having an opening at one end and a central longitudinal axis passing through the opening. The reflector has an internal reflective surface surrounding the axis and providing multiple focal points substantially along the axis from which light emanating from the compact fluorescent lamp can be reflected by the surface through the opening. There is a lens at or adjacent to the opening through which the reflected light passes.

摘要翻译： 用于紧凑型荧光灯的反射器/集中器包括凹形反射器，其尺寸适于保持紧凑型荧光灯，并且在一端具有开口，并且具有穿过开口的中心纵向轴线。 反射器具有围绕轴线的内部反射表面，并且基本上沿轴线提供多个焦点，从紧凑型荧光灯发出的光可以从该轴通过开口被表面反射。 反射光通过的开口处或与其相邻的透镜。

公开(公告)号：US20110230145A1

公开(公告)日：2011-09-22

申请号：US13117710

申请日：2011-05-27

申请人： Lysander Lim ,  David Pehlke ,  John Khoury ,  Vincent Leung

发明人： Lysander Lim ,  David Pehlke ,  John Khoury ,  Vincent Leung

IPC分类号： H04W52/04

CPC分类号： H04W52/52

摘要： In one embodiment, a method includes detecting a power level of a power amplifier coupled to a transceiver during a current burst of a radio communication and providing the detected power level from the power amplifier to the transceiver and controlling a power level of the power amplifier during a next burst based on the detected power level of the current burst.

摘要翻译： 在一个实施例中，一种方法包括检测在无线电通信的当前突发期间耦合到收发器的功率放大器的功率电平，并且将检测到的功率电平从功率放大器提供给收发器，并且控制功率放大器的功率电平 基于当前突发的检测到的功率电平的下一脉冲串。

公开(公告)号：US07598769B2

公开(公告)日：2009-10-06

申请号：US11675590

申请日：2007-02-15

申请人： Vincent Leung

发明人： Vincent Leung

IPC分类号： H03K19/173

CPC分类号： H03K19/17784 ,  H03K19/17728 ,  H03K19/17792

摘要： A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2N configuration bit inputs and a Look Up Table output. The first stage of the Look Up Table includes 2N tri-state buffers coupled to receive the 2N configuration bit inputs respectively. A decoder, configured from logic gates, is coupled to receive to one or more Look Up Table select signals and to generate a set of control signals to control the 2N tri-state buffers so that one or more of the 2N configuration bit inputs is selected by the first stage. The configuration bits are then provided to subsequent muxing stages in the Look Up Table.

摘要翻译： 一种包括以阵列组织的多个逻辑元件的可编程逻辑器件。 每个逻辑元件包括具有2N个配置位输入和查找表输出的N阶查找表结构。 查找表的第一级包括2N个三态缓冲器，分别耦合以接收2N个配置位输入。 由逻辑门配置的解码器被耦合以接收一个或多个查找表选择信号并产生一组控制信号以控制2N个三态缓冲器，使得选择2N个配置位输入中的一个或多个 在第一阶段。 然后，配置位将提供给查找表中的后续多路复用阶段。

公开(公告)号：US20080076378A1

公开(公告)日：2008-03-27

申请号：US11646055

申请日：2006-12-27

申请人： Lysander Lim ,  David Pehlke ,  John Khoury ,  Vincent Leung

发明人： Lysander Lim ,  David Pehlke ,  John Khoury ,  Vincent Leung

IPC分类号： H04B1/16

CPC分类号： H04W52/52

摘要： In one embodiment, a method includes detecting a power level of a power amplifier coupled to a transceiver during a current burst of a radio communication and providing the detected power level from the power amplifier to the transceiver and controlling a power level of the power amplifier during a next burst based on the detected power level of the current burst.

摘要翻译： 在一个实施例中，一种方法包括检测在无线电通信的当前突发期间耦合到收发器的功率放大器的功率电平，并且将检测到的功率电平从功率放大器提供给收发器，并且控制功率放大器的功率电平 基于当前突发的检测到的功率电平的下一脉冲串。

公开(公告)号：US06296370B1

公开(公告)日：2001-10-02

申请号：US09369552

申请日：1999-08-06

申请人： David Bamber ,  Vincent Leung

发明人： David Bamber ,  Vincent Leung

IPC分类号： F21L400

CPC分类号： F21V33/00 ,  F21L2/00 ,  F21V33/0056

摘要： A multi-function modular storage light unit including a primary housing unit and detachable modules such as a radio and an auxiliary flashlight. The primary housing unit contains a spotlight, a power switch, and a handle to carry the unit. There is also a storage compartment built into the primary housing unit. The modules preferably include belt clips for hands-free transport. The modules are removably attached to the primary unit by way of an attachment mechanism which may include alignment features and a latching mechanism. The modules may alternatively be removably attached by their belt clips to sleeves arranged on the primary housing. Each of the detachable modules and the spotlight is independently powered.

摘要翻译： 一种多功能模块化存储灯单元，包括主壳体单元和诸如无线电和辅助手电筒的可拆卸模块。 主要壳体单元包含一个聚光灯，一个电源开关和一个手柄来承载本机。 主要外壳单元内还有一个储藏室。 模块优选地包括用于免提运输的带夹。 模块通过可包括对准特征和锁定机构的附接机构可移除地附接到主单元。 模块可以可选地通过其带夹可移除地附接到布置在主壳体上的套筒。 每个可拆卸模块和聚光灯都是独立供电的。

公开(公告)号：US5978267A

公开(公告)日：1999-11-02

申请号：US175647

申请日：1998-10-20

申请人： Pau-Ling Chen ,  Michael Van Buskirk ,  Shane C. Hollmer ,  Michael S. C. Chung ,  Binh Quang Le ,  Vincent Leung ,  Shoichi Kawamura ,  Masaru Yano

发明人： Pau-Ling Chen ,  Michael Van Buskirk ,  Shane C. Hollmer ,  Michael S. C. Chung ,  Binh Quang Le ,  Vincent Leung ,  Shoichi Kawamura ,  Masaru Yano

IPC分类号： G11C16/02 ,  G11C7/12 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C7/12

摘要： In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.

摘要翻译： 在非易失性存储器件（例如NAND闪速存储器件100）的编程中，将正偏置电压Vbias施加到位线44以将相应的存储器栅极44a设置为编程状态。 在另一实施例中，通过使用串联连接的两个电阻器56和58分压选择漏极栅极电压Vcc来获得正偏置电压Vbias。

公开(公告)号：US07974596B2

公开(公告)日：2011-07-05

申请号：US11646055

申请日：2006-12-27

申请人： Lysander Lim ,  David Pehlke ,  John Khoury ,  Vincent Leung

发明人： Lysander Lim ,  David Pehlke ,  John Khoury ,  Vincent Leung

IPC分类号： H01Q11/12 ,  H04B1/04

CPC分类号： H04W52/52

摘要： In one embodiment, a method includes detecting a power level of a power amplifier coupled to a transceiver during a current burst of a radio communication and providing the detected power level from the power amplifier to the transceiver and controlling a power level of the power amplifier during a next burst based on the detected power level of the current burst.

摘要翻译： 在一个实施例中，一种方法包括检测在无线电通信的当前突发期间耦合到收发器的功率放大器的功率电平，并且将检测到的功率电平从功率放大器提供给收发器，并且控制功率放大器的功率电平 基于当前突发的检测到的功率电平的下一脉冲串。