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公开(公告)号：US4240195A
公开(公告)日：1980-12-23
申请号：US942861
申请日：1978-09-15
IPC分类号： G11C14/00 , G11C11/40 , H01L21/768 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/535 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108 , B01J17/00
CPC分类号： H01L27/10844 , H01L21/768 , H01L23/535 , H01L27/10805 , H01L2924/0002
摘要： A memory in which each cell comprises an MOS transistor merged with a storage capacitor and in which the cells are arranged to permit adjacent pairs of transistors in a common column to share a common source and the transistors in a common row to share a common gate electrode conductor. The memory uses a first polycrystalline silicon layer which is patterned to provide interconnected storage electrodes and a second polycrystalline silicon layer which is patterned to provide a plurality of stripes to serve as the bit sense lines and a plurality of gate electrodes.
摘要翻译： 一种存储器，其中每个单元包括与存储电容器合并的MOS晶体管，其中所述单元被布置成允许公共列中的相邻晶体管共享公共源，并且共用行中的晶体管共享公共栅电极 导体。 存储器使用图案化以提供互连的存储电极的第一多晶硅层和被图案化以提供多个条纹以用作位感测线和多个栅电极的第二多晶硅层。
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公开(公告)号：US4999507A
公开(公告)日：1991-03-12
申请号：US521765
申请日：1990-05-10
申请人： James T. Clemens , Shane Y. Hong
发明人： James T. Clemens , Shane Y. Hong
IPC分类号： H01L21/673 , H01L21/683
CPC分类号： H01L21/67396 , H01L21/6831 , H01L21/6833 , Y10T279/23
摘要： Disclosed is apparatus comprising an electrostatic cassette assembly for securing a semiconductor wafer during lithographic processing such as direct-write particle-beam lithography. The cassette assembly comprises a cassette body and an electrostatic chuck installable in, and removeable from, the cassette body. The electrostatic chuck comprises a charge plate having a thin dielectric layer on its upper surface, against which the wafer is flattened by Coulombic force. Charge storage means are included for maintaining an electrical potential difference between the wafer and the charge plate even in the absence of connection to a source of electrical energy external to the assembly.
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公开(公告)号：US6038163A
公开(公告)日：2000-03-14
申请号：US189131
申请日：1998-11-09
IPC分类号： H01L27/11 , G11C11/412 , G11C11/413 , H01L21/8244 , G11C11/00
CPC分类号： G11C11/412
摘要： An apparatus and method for constructing a capacitor loaded memory cell. This capacitor loaded memory cell operates as a static random access memory (SRAM) cell if a particular capacitor and transistor configuration is used. Normally, capacitors are not an obvious choice as a load device for a memory cell because the intrinsic nature of capacitors is one that blocks the flow of direct current, the invention takes into account the secondary effects such as leakage of a particular dielectric used in the construction of the capacitor to modify the current blocking nature of the capacitor.
摘要翻译： 一种用于构造电容器存储单元的装置和方法。 如果使用特定的电容器和晶体管配置，该电容器加载的存储单元作为静态随机存取存储器（SRAM）单元工作。 通常，电容器作为存储器单元的负载装置不是明显的选择，因为电容器的固有特性是阻止直流电流的本征特性，本发明考虑到二次效应，例如在 电容器的构造来修改电容器的电流阻塞性质。
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公开(公告)号：US06272039B1
公开(公告)日：2001-08-07
申请号：US09498543
申请日：2000-02-04
IPC分类号： G11C1100
CPC分类号： G11C11/412
摘要： An apparatus and method for constructing a temperature insensitive memory cell. This temperature insensitive memory cell operates as a static random access memory (SRAM) cell if a particular capacitor and transistor configuration is used. The temperature insensitive memory cell apparatus includes at least one transistor having a current leakage, and at least one capacitor electrically connected to the transistor. The capacitor acts as a load element for the memory cell. The capacitor has a temperature dependent capacitor leakage that tracks the current leakage of transistor as said at least one transistor as the transistor varies with temperature.
摘要翻译： 一种用于构建温度不敏感的存储单元的装置和方法。 如果使用特定的电容器和晶体管配置，该温度不敏感的存储器单元作为静态随机存取存储器（SRAM）单元工作。 温度不敏感的存储单元装置包括至少一个具有电流泄漏的晶体管，以及电连接到该晶体管的至少一个电容器。 电容器用作存储单元的负载元件。 电容器具有依赖于温度的电容器泄漏，其随着晶体管随着温度变化而跟踪晶体管的电流泄漏作为所述至少一个晶体管。
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5.发明授权
公开(公告)号：US4216489A
公开(公告)日：1980-08-05
申请号：US5639
申请日：1979-01-22
IPC分类号： G11C11/35 , G11C11/404 , H01L27/108 , H01L27/02
CPC分类号： G11C11/404 , G11C11/35 , H01L27/10805 , Y10S148/07
摘要： In a dynamic MOS (Metal Oxide Semiconductor) random access memory, reverse bias leakage currents which deplete stored charges are reduced by minimizing minority carrier generation-type currents. By so minimizing these currents, the leakage currents become dominated by minority carrier diffusion currents. The memory is ideally formed in an upper semiconductor layer (14) of a layered structure (11). The semiconductor layer (14) is grown epitaxially with a relatively low dopant concentration on a semiconductor substrate (12) with a dopant concentration of the same conductivity type and about three orders of magnitude greater than that of the epitaxially grown layer. The epitaxially grown structure is advantageously suited for the memory circuits in that it may be formed with very low leakage currents. The material further offers by its layered structure a basis for optimizing dynamic memory device characteristics.
摘要翻译： 在动态MOS（金属氧化物半导体）随机存取存储器中，通过最小化少数载流子产生型电流来减少耗尽存储电荷的反向偏置漏电流。 通过如此最小化这些电流，泄漏电流成为少数载流子扩散电流的主导。 存储器理想地形成在层状结构（11）的上半导体层（14）中。 在半导体衬底（12）上以相对低的掺杂剂浓度外延生长半导体层（14），其掺杂浓度相同，并且比外延生长层大约三个数量级。 外延生长的结构有利地适用于存储器电路，因为其可以形成非常低的漏电流。 该材料通过其分层结构进一步提供了优化动态存储器件特性的基础。
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公开(公告)号：US5073716A
公开(公告)日：1991-12-17
申请号：US626930
申请日：1990-12-12
申请人： James T. Clemens , Shane Y. Hong
发明人： James T. Clemens , Shane Y. Hong
IPC分类号： H01J37/20 , H01L21/673 , H01L21/683
CPC分类号： H01L21/6833 , H01J37/20 , H01L21/67386 , H01L21/6831
摘要： Disclosed is apparatus comprising an electrostatic cassette assembly for securing a semiconductor wafer during lithographic processing such as direct-write particle-beam lithography. The cassette assembly comprises a cassette body and an electrostatic chuck installable in, and removeable from, the cassette body. The electrostatic chuck comprises a charge plate having a thin dielectric layer on its upper surface, against which the wafer is flattened by Coulombic force. Charge storage means are included for maintaining an electrical potential difference between the wafer and the charge plate even in the absence of connection to a source of electrical energy external to the assembly.
摘要翻译： 公开了包括用于在诸如直写式粒子束光刻的光刻处理期间固定半导体晶片的静电盒组件的装置。 盒式组件包括可装在盒体中并可从盒体移除的盒体和静电吸盘。 静电卡盘包括在其上表面上具有薄介电层的充电板，晶片通过库仑力平坦化。 包括电荷存储装置，用于维持晶片和充电板之间的电位差，即使在不连接到组件外部的电能源的情况下。
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公开(公告)号：US4291322A
公开(公告)日：1981-09-22
申请号：US61664
申请日：1979-07-30
申请人： James T. Clemens , Kay M. Locke
发明人： James T. Clemens , Kay M. Locke
IPC分类号： H01L21/768 , H01L29/08 , H01L29/78 , H01L29/04 , H01L23/48
CPC分类号： H01L29/0847 , H01L21/76877
摘要： A contact structure and method of fabrication for achieving shallow junction MOS integrated circuits. An insulator (23) such as phosphosilicate glass is deposited over the circuit and contact windows (24 and 25) opened therein. Fire polishing of the glass is eliminated so that the junctions can be made shallow and the sides of the windows remain steep. A layer of polycrystalline silicon (26) is deposited over the insulator and the contact windows so as to conformally coat the sides of the windows and the exposed semiconductor. A contact metal (28 and 29), such as aluminum, is deposited over the polycrystalline silicon. The metal tends to be essentially discontinuous over the steep sides of the windows, but the polycrystalline silicon layer has sufficiently low resistivity to provide adequate conduction in these areas.
摘要翻译： 用于实现浅结MOS集成电路的接触结构和制造方法。 诸如磷硅玻璃的绝缘体（23）沉积在电路上并且接触在其中打开的窗口（24和25）。 消除玻璃的火抛光，使得接头可以变浅并且窗口的侧面保持陡峭。 一层多晶硅（26）沉积在绝缘体和接触窗口上，以便共形地覆盖窗户和暴露的半导体的侧面。 诸如铝的接触金属（28和29）沉积在多晶硅上。 金属倾向于在窗口的陡峭侧面上基本上不连续，但是多晶硅层具有足够低的电阻率以在这些区域中提供足够的导电性。
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