-
公开(公告)号：US5166562A
公开(公告)日：1992-11-24
申请号：US697410
申请日：1991-05-09
CPC分类号： G05F1/468 , G05F3/24 , G11C11/56 , G11C11/5621 , G11C27/005 , G11C5/147 , G11C16/30 , G11C2211/5634 , G11C7/16
摘要： A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A follower amplifier is connected to each floating gate storage device and drives an analog output voltage bus. A capacitor is connected to each analog output storage bus. An analog pass gate is connected between each analog output voltage bus and a common monitor/dynamic load bus. Each analog pass gate is driven by a strobe signal.
摘要翻译： 用于产生用于参考或偏置使用的N个模拟电压信号的电路使用N个模拟浮动栅极存储装置。 提供电子注入电路用于将电子注入到上面，并且提供隧道结构用于从每个浮动栅极存储装置的浮动栅极去除电子。 跟随放大器连接到每个浮动栅极存储装置并驱动模拟输出电压总线。 电容器连接到每个模拟输出存储总线。 每个模拟输出电压总线和公共监视器/动态负载总线之间连接一个模拟传输门。 每个模拟传输门由选通信号驱动。
-
公开(公告)号：US5303329A
公开(公告)日：1994-04-12
申请号：US805324
申请日：1991-12-10
CPC分类号： G06N3/0635
摘要： A continuous weight-update device for a synaptic element including at least one MOS transistor comprises a floating node having a capacitance associated therewith, the floating gate comprising at least a part of the floating node, first and second input lines, first and second error lines, an electron tunneling structure coupled to the floating node for tunneling electrons from the floating node, and an electron injecting structure coupled to the floating node for injecting electrons onto the floating node. Control circuitry is responsive to signals on the first input and error lines, for activating the electron tunneling structure, and control circuitry is responsive to signals on the second input and error lines, for activating the electron injecting structure. Circuitry is provided for driving signals onto the first and second input and error lines. Both a single synapse and an array of synapses incorporating the continuous weight-update device are also taught.
摘要翻译： 用于包括至少一个MOS晶体管的突触元件的连续加权更新装置包括具有与其相关联的电容的浮动节点，所述浮动栅极包括浮动节点的至少一部分，第一和第二输入线，第一和第二误差线 耦合到浮动节点的电子隧道结构用于从浮动节点隧穿电子，以及耦合到浮动节点的电子注入结构，用于将电子注入到浮动节点上。 控制电路响应于第一输入和错误线上的信号，用于激活电子隧道结构，并且控制电路响应于第二输入和错误线上的信号，用于激活电子注入结构。 提供电路用于将信号驱动到第一和第二输入和错误线上。 还教导了包含连续加权更新装置的单一突触和突触阵列。
-
公开(公告)号：US5160899A
公开(公告)日：1992-11-03
申请号：US781503
申请日：1991-10-22
CPC分类号： G06N3/063 , H01L27/0629 , H03F1/0261 , H03F1/303 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： An adaptable current mirror includes first and second MOS transistors. The first MOS transistor has its gate connected to its drain. A MOS capacitor structure is connected in series between the gate of the first MOS transistor and the gate of the second MOS transistor. Electrons may be placed onto and removed in an analog manner from a floating node associated with the second MOS transistor, usually the gate of the transistor, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure. A plurality of adaptable current mirrors communicating with a plurality of current-carrying lines may be employed for indicating the output of the one of the plurality of current-carrying lines through which the most current is flowing.
摘要翻译： 适应电流镜包括第一和第二MOS晶体管。 第一个MOS晶体管的栅极连接到其漏极。 MOS电容器结构串联连接在第一MOS晶体管的栅极和第二MOS晶体管的栅极之间。 电子可以通过施加第一和第二电气控制信号，以模拟方式从与第二MOS晶体管（通常是晶体管的栅极）相关联的浮动节点放置和去除。 第一电控信号控制电子从电子注入结构注入到浮动节点上，第二电控信号通过电子去除结构控制从浮动节点去除电子。 可以采用与多个载流线路通信的多个适应电流镜，以指示最流动的多个通电线路中的一个的输出。
-
公开(公告)号：US5243554A
公开(公告)日：1993-09-07
申请号：US961785
申请日：1992-10-15
CPC分类号： G11C11/5621 , G05F1/468 , G05F3/24 , G11C11/56 , G11C27/005 , G11C5/147 , G11C16/30 , G11C2211/5634 , G11C7/16
摘要： A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A follower amplifier is connected to each floating gate storage device and drives an analog output voltage bus. A capacitor is connected to each analog output storage bus. An analog pass gate is connected between each analog output voltage bus and a common monitor/dynamic load bus. Each analog pass gate is driven by a strobe signal.
摘要翻译： 用于产生用于参考或偏置使用的N个模拟电压信号的电路使用N个模拟浮动栅极存储装置。 提供电子注入电路用于将电子注入到上面，并且提供隧道结构用于从每个浮动栅极存储装置的浮动栅极去除电子。 跟随放大器连接到每个浮动栅极存储装置并驱动模拟输出电压总线。 电容器连接到每个模拟输出存储总线。 每个模拟输出电压总线和公共监视器/动态负载总线之间连接一个模拟传输门。 每个模拟传输门由选通信号驱动。
-
公开(公告)号：US5120996A
公开(公告)日：1992-06-09
申请号：US535283
申请日：1990-06-06
CPC分类号： G11C27/024 , G06N3/063 , G11C11/54
摘要： An electronic circuit is disclosed having a sample/hold amplifier connected to an adaptive amplifier. A plurality of such electronic cicuits may be configured in an array of rows and columns. An input voltage vector may be compared with an analog voltage vector stored in a row or column of the array and the stored vector closest to the applied input vector may be identified and further processed.
摘要翻译： 公开了一种具有连接到自适应放大器的采样/保持放大器的电子电路。 多个这样的电子线路可以被配置成行和列的阵列。 可以将输入电压矢量与存储在阵列的行或列中的模拟电压矢量进行比较，并且可以识别并进一步处理最接近所施加的输入向量的存储向量。
-
公开(公告)号：US5119038A
公开(公告)日：1992-06-02
申请号：US650577
申请日：1991-02-04
CPC分类号： H03F1/303 , G06N3/063 , H01L27/0629 , H03F1/0261 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： An MOS current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures in order to adapt the current mirror to supply a desired output current when a particular input calibration current is present.
摘要翻译： MOS电流镜包括浮动节点，在该浮动节点上，可以通过控制信号和电半导体结构从中传输电子，以便在存在特定输入校准电流时使电流镜适应于提供期望的输出电流。
-
公开(公告)号：US5083044A
公开(公告)日：1992-01-21
申请号：US357520
申请日：1989-05-25
摘要： An electronic circuit is disclosed having a sample/hold amplifier connected to an adaptive amplifier. A plurality of such electronic circuits may be configured in an array of rows and columns. An input voltage vector may be compared with an analog voltage vector stored in a row or column of the array and the stored vector closest to the applied input vector may be identified and further processed.
摘要翻译： 公开了一种具有连接到自适应放大器的采样/保持放大器的电子电路。 多个这样的电子电路可以被配置成行和列的阵列。 可以将输入电压矢量与存储在阵列的行或列中的模拟电压矢量进行比较，并且可以识别并进一步处理最接近所施加的输入向量的存储向量。
-
公开(公告)号：US4953928A
公开(公告)日：1990-09-04
申请号：US363678
申请日：1989-06-09
IPC分类号： H01L29/788 , H01L29/861
CPC分类号： H01L29/7885 , H01L29/7887 , H01L29/8616
摘要： A semiconductor structure for long-term learning includes a p-type silicon substrate or well having first and second spaced apart n-type regions formed therein. A polysilicon floating gate is separated from the surface of the silicon substrate by a layer of gate oxide. One edge of the polysilicon floating gate is aligned with the edge of the first n-type region such that the polysilicon floating gate does not appreciably overly the n-type region. The second n-type region lies beyond the edge of the polysilicon floating gate. The first n-type region, the silicon substrate, and the second n-type region form the collector, base, and emitter, respectively, of a lateral bipolar transistor.An alternate embodiment of a semiconductor long-term learning structure includes an n-type silicon substrate having a p-well region formed therein. An n-type region is formed within the well region. A polysilicon floating gate is separated from the surface of the silicon substrate by a gate oxide and is positioned above the well region. One edge of the polysilicon floating gate is aligned with the edge of the n-type region within the well region such that the polysilicon floating gate does not appreciably overly the n-type region. The substrate, the well, and the n-type region, respectively, form the emitter, base, and collector of a bipolar transistor.
摘要翻译： 用于长期学习的半导体结构包括在其中形成有第一和第二间隔开的n型区的p型硅衬底或阱。 多晶硅浮栅通过一层栅极氧化物与硅衬底的表面分离。 多晶硅浮动栅极的一个边缘与第一n型区域的边缘对准，使得多晶硅浮置栅极不明显地超过n型区域。 第二n型区域位于多晶硅浮栅的边缘之上。 第一n型区域，硅衬底和第二n型区域分别形成横向双极晶体管的集电极，基极和发射极。 半导体长期学习结构的替代实施例包括其中形成有p阱区的n型硅衬底。 在阱区内形成n型区域。 多晶硅浮置栅极通过栅极氧化物与硅衬底的表面分离并且位于阱区域之上。 多晶硅浮置栅极的一个边缘与阱区域内的n型区域的边缘对齐，使得多晶硅浮栅不明显地超过n型区域。 衬底，阱和n型区域分别形成双极晶体管的发射极，基极和集电极。
-
公开(公告)号：US5331215A
公开(公告)日：1994-07-19
申请号：US922535
申请日：1992-07-30
申请人： Timothy P. Allen , Janeen D. W. Anderson , Carver A. Mead , Federico Faggin , John C. Platt , Michael F. Wall
发明人： Timothy P. Allen , Janeen D. W. Anderson , Carver A. Mead , Federico Faggin , John C. Platt , Michael F. Wall
CPC分类号： H03F1/303 , G06N3/063 , H01L27/0629 , H03F1/0261 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： A synaptic array according to the present invention comprises a plurality of electrically-adaptable elements. Electrons may be placed onto and removed from a floating node in each electrically adaptable element associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals generated in response to an adapt signal. The inputs to all synaptic elements in a row are connected to a common row input line. Adapt inputs to all synaptic elements in a column are connected together to a common column adapt line. The current supplied to all amplifiers in a column is commonly provided by a sense line. In order to adapt the synaptic elements in the M row by N column matrix of the present invention, the voltages to which a given column n of the matrix is to be adapted are placed onto the input voltage lines, and the synaptic elements in column n are then simultaneously adapted by assertion of an adapt signal on the adapt line for column n. The vectors of input voltages for adapting successive columns may be placed sequentially onto the row input voltage lines and used to adapt the columns of synaptic elements by assertion of the adapt signals on the appropriate column adapt lines until the entire array is electrically adapted. After each synaptic element has been adapted, the current flowing through it will be maximized when the voltage at the input of the synaptic element equals the voltage to which the synaptic element has been adapted. An electrically adaptable winner-take-all circuit has its inputs connected to the column-sense lines of the array.
摘要翻译： 根据本发明的突触阵列包括多个电适应元件。 可以通过施加产生的第一和第二电控制信号将电子放置在与至少一个MOS绝缘栅场效应晶体管（通常是晶体管的栅极）相关联的每个电适应元件中的浮动节点上并从其移除， 响应于适配信号。 对一行中所有突触元素的输入连接到公共行输入行。 将输入到列中的所有突触元素的调整连接到公共列适应线。 提供给列中所有放大器的电流通常由感测线提供。 为了适应本发明的M行×N列矩阵中的突触元素，要将矩阵的给定列n适应的电压放置在输入电压线上，并且列n中的突触元素 然后通过在第n列的适应线上断言适配信号同时进行调整。 用于适配连续列的输入电压的矢量可以顺序地放置在行输入电压线上，并且用于通过在适当的列适配线上断言适配信号来适应突触元件的列，直到整个阵列电气适配。 在每个突触元件已经适应之后，当突触元件的输入端的电压等于突触元件适应的电压时，流过它的电流将被最大化。 电气适应性的胜者总线电路的输入连接到阵列的列感测线。
-
10.发明授权
公开(公告)号：US5204549A
公开(公告)日：1993-04-20
申请号：US827005
申请日：1992-01-28
IPC分类号： G06N3/063
CPC分类号： G06N3/0635
摘要： A weight-storage and weight-adjustment circuit includes a first hot electron injection device coupled to a first floating gate and a second hot electron injection device coupled to the second floating gate. The floating gates are associated with two series connected MOS transistors. The first and second hot electron injection devices comprise gated lateral bipolar transistors. The weight may be decreased by injecting hot electrons from the first hot electron injection device onto the first floating gate to decrease the first analog voltage and increased by injecting electrons from the second hot electron injection device onto the second floating gate to decrease the second analog voltage. Circuitry are provided to periodically adjust the absolute voltage levels on the first and second floating gates to prevent them from becoming too negative over time. First and second electron tunneling devices are coupled to the first and second floating gates, respectively, to simultaneously adjust the voltages stored on the floating gates to keep them within a desired voltage range.
摘要翻译： 重量存储和重量调节电路包括耦合到第一浮动栅极的第一热电子注入装置和耦合到第二浮动栅极的第二热电子注入装置。 浮动栅极与两个串联的MOS晶体管相关联。 第一和第二热电子注入装置包括门控侧向双极晶体管。 可以通过将热电子从第一热电子注入装置注入到第一浮动栅极上来减小第一模拟电压并通过将电子从第二热电子注入装置注入到第二浮栅上来增加，从而减小第二模拟电压 。 提供电路以周期性地调整第一和第二浮动栅极上的绝对电压电平，以防止它们随时间变得太负。 第一和第二电子隧穿装置分别耦合到第一和第二浮动栅极，以同时调节存储在浮动栅极上的电压以将它们保持在期望的电压范围内。
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.022 秒)
