Magnetic memory device and method for controlling a write pulse

    公开(公告)号:US11031062B2

    公开(公告)日:2021-06-08

    申请号:US16603343

    申请日:2018-04-04

    摘要: According to one embodiment, a magnetic memory device includes a stacked body and a controller. The stacked body includes a first conductive layer, a second conductive layer, a first magnetic layer provided between the first conductive layer and the second conductive layer, a second magnetic layer provided between the first magnetic layer and the second conductive layer, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. A resistance value per unit area of the nonmagnetic layer exceeds 20 Ωμm2. The controller is electrically connected to the first conductive layer and the second conductive layer, and supplies a write pulse to the stacked body in a first operation. The write pulse includes a rise period, a potential of the write pulse changing from a first potential toward a second potential in the rise period, an intermediate period of the second potential after the rise period, and a fall period after the intermediate period, the potential of the write pulse changing from the second potential toward the first potential in the fall period. A duration of the fall period is longer than a duration of the rise period.

    HIGH-FREQUENCY PHASE-LOCKED OSCILLATION CIRCUIT

    公开(公告)号:US20180302035A1

    公开(公告)日:2018-10-18

    申请号:US15569500

    申请日:2016-04-27

    摘要: The present invention provides a high-frequency phase-locked oscillation circuit having an extremely narrow peak width and a stable frequency so that a high-frequency wave that is oscillated by the MR element solves a problem of a large peak width of oscillation spectrum. The high-frequency phase-locked oscillation circuit is achieved by providing: a magnetoresistive element 6 that oscillates a high-frequency wave with an oscillating frequency fout; a reference signal source 1 that outputs a reference signal with a reference frequency fref; a phase-locked loop circuit having a phase comparator 3, a loop filer 4, and a frequency divider 9; an adder 5 that adds a phase error signal A output from the loop filter and a bias voltage B for oscillating the high-frequency wave from the magnetoresistive element, and that inputs an added bias voltage (A+B) to the magnetoresistive element 6; and a filter 7 provided between the frequency divider 9 and the magnetoresistive element 6 in a region closer to an input side of the frequency divider 9, the filter cutting off the reference frequency fref while allowing the oscillating frequency fout to pass through the filter.