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    Technique for receiving differential multi-PAM signals
    9.
    发明申请
    Technique for receiving differential multi-PAM signals 有权
    接收差分多PAM信号的技术

    公开(公告)号：US20050069067A1

    公开(公告)日：2005-03-31

    申请号：US10673677

    申请日：2003-09-30

    申请人： Jared Zerbe ,  Grace Tsang ,  Mark Horowitz ,  Bruno Garlepp ,  Carl Werner

    发明人： Jared Zerbe ,  Grace Tsang ,  Mark Horowitz ,  Bruno Garlepp ,  Carl Werner

    IPC分类号： H04L25/49 ,  H04L27/06

    CPC分类号： H04L25/4917

    摘要： A technique for receiving differential multi-PAM signals is disclosed. In one particular exemplary embodiment, the technique may be realized as a differential multi-PAM extractor circuit. In this particular exemplary embodiment, the differential multi-PAM extractor circuit comprises an upper LSB sampler circuit configured to receive a differential multi-PAM input signal and a first differential reference signal, and to generate a first differential sampled output signal. The differential multi-PAM extractor circuit also comprises a lower LSB sampler circuit configured to receive the differential multi-PAM input signal and a second differential reference signal, and to generate a second differential sampled output signal. The differential multi-PAM extractor circuit further comprises a combiner circuit configured to receive the first differential sampled output signal and the second differential sampled output signal, and to generate a differential LSB output signal indicating an LSB value of the differential multi-PAM input signal.

    摘要翻译： 公开了一种用于接收差分多PAM信号的技术。 在一个特定的示例性实施例中，该技术可以被实现为差分多PAM提取器电路。 在该特定示例性实施例中，差分多PAM提取器电路包括被配置为接收差分多PAM输入信号和第一差分参考信号的高LSB采样器电路，并且产生第一差分采样输出信号。 差分多PAM提取器电路还包括被配置为接收差分多PAM输入信号和第二差分参考信号的低LSB采样器电路，并且产生第二差分采样输出信号。 差分多PAM提取器电路还包括组合器电路，其被配置为接收第一差分采样输出信号和第二差分采样输出信号，并且产生指示差分多PAM输入信号的LSB值的差分LSB输出信号。

    Circuit, apparatus and method for adjusting a duty-cycle of a clock signal in response to incoming serial data
    10.
    发明授权
    Circuit, apparatus and method for adjusting a duty-cycle of a clock signal in response to incoming serial data 失效
    响应于输入的串行数据调整时钟信号的占空比的电路，装置和方法

    公开(公告)号：US07298807B2

    公开(公告)日：2007-11-20

    申请号：US10672853

    申请日：2003-09-26

    申请人： Jared Zerbe ,  Mark Horowitz ,  Carl Werner

    发明人： Jared Zerbe ,  Mark Horowitz ,  Carl Werner

    IPC分类号： H04L7/00

    CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C2207/2254 ,  H03L7/07 ,  H03L7/087 ,  H03L7/091 ,  H04L7/033

    摘要： A circuit, apparatus and method for maximizing system margins by adjusting a duty-cycle of a clock signal in a receive circuit to whatever duty-cycle is optimal for the particular incoming serial data, rather than the typical 50% duty-cycle, is provided in embodiments of the present invention. A receive circuit, including duty-cycle-correction logic, is included in a double-data rate communication apparatus having a transmit circuit transmitting serial data having duty-cycle distortion. A receive circuit includes a first and second sampler to obtain data and edge values of an incoming serial data responsive to a data and edge clock, respectively. A duty-cycle-correction logic generates a duty-cycle-correction signal to a duty-cycle clock integrator that adjusts the edge clock signals while maintaining quadrature to the data clocks. In an embodiment of the present invention, a duty-cycle-correction logic includes an evaluator circuit to generate an up or down signal responsive to the data and/or edge values. In a further embodiment of the present invention, an evaluator circuit is coupled to a counter and a DAC to generate a duty-cycle-correction signal to the duty-cycle clock integrator. A digital filter or coding scheme is also used to reduce the likelihood of misinterpreting malevolent incoming serial data for duty-cycle distortion in an embodiment of the present invention.

    摘要翻译： 通过将接收电路中的时钟信号的占空比调整到任何占空比来最大化系统裕度的电路，装置和方法对于特定的输入串行数据而言不是典型的50％占空比是最佳的 在本发明的实施例中。 包括占空比校正逻辑的接收电路被包括在具有发送电路的双数据速率通信装置中，该发送电路发送具有占空比失真的串行数据。 接收电路包括第一和第二采样器，用于分别响应于数据和边沿时钟获得输入串行数据的数据和边缘值。 占空比校正逻辑产生占空比校正信号到占空比时钟积分器，该占空比校正信号调整边沿时钟信号同时保持与数据时钟的正交。 在本发明的实施例中，占空比校正逻辑包括响应于数据和/或边缘值产生上升或下降信号的评估器电路。 在本发明的另一实施例中，评估器电路耦合到计数器和DAC，以向占空比时钟积分器产生占空比校正信号。 数字滤波器或编码方案也用于在本发明的一个实施例中减少对恶意输入串行数据进行占空比失真的误解的可能性。