公开(公告)号：US20050167786A1

公开(公告)日：2005-08-04

申请号：US10708023

申请日：2004-02-03

申请人： Jason Gill ,  Terence Hook ,  Randy Mann ,  William Murphy ,  William Tonti ,  Steven Voldman

发明人： Jason Gill ,  Terence Hook ,  Randy Mann ,  William Murphy ,  William Tonti ,  Steven Voldman

IPC分类号： H01L21/8244 ,  H01L27/02 ,  H01L27/08 ,  H01L27/11 ,  H01L27/12 ,  H01L27/082

CPC分类号： H01L27/11 ,  H01L27/0288 ,  H01L27/0802 ,  H01L27/1112 ,  H01L27/1203 ,  H01L29/7304 ,  H01L29/7378 ,  H01L29/7391 ,  H01L29/78 ,  Y10S257/903 ,  Y10S257/904

摘要： A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.

摘要翻译： 一种用于形成具有优异的ESD保护特性的半导体器件的方法和系统。 电阻材料层设置在触头螺柱上下表面中的至少一个上的接触孔内。 在优选实施例中，积分电阻器的电阻值介于约1欧姆至约10欧姆之间，或10欧姆至100欧姆之间。 电阻层的实施例包括溅射硅材料，隧道氧化物，隧道氮化物，硅注入氧化物，注入硅的氮化物或非晶多晶硅。 本发明的实施例包括SRAM，双极晶体管，SOI横向二极管，MOSFET和SiGe晶体管。

公开(公告)号：US20080042798A1

公开(公告)日：2008-02-21

申请号：US11848263

申请日：2007-08-31

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Terence Hook ,  Robert Rassel ,  Edmund Sprogis ,  Anthony Stamper ,  William Murphy

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Terence Hook ,  Robert Rassel ,  Edmund Sprogis ,  Anthony Stamper ,  William Murphy

IPC分类号： H01C1/08

CPC分类号： H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

公开(公告)号：US20060152333A1

公开(公告)日：2006-07-13

申请号：US10905546

申请日：2005-01-10

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Terence Hook ,  Robert Rassel ,  Edmund Sprogis ,  Anthony Stamper ,  William Murphy

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Terence Hook ,  Robert Rassel ,  Edmund Sprogis ,  Anthony Stamper ,  William Murphy

IPC分类号： H01C1/08

CPC分类号： H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

摘要翻译： 提供带散热片的电阻。 散热器包括具有导热性高的金属或其它热导体的导电路径。 为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。 因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。 除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

公开(公告)号：US20060205098A1

公开(公告)日：2006-09-14

申请号：US10906826

申请日：2005-03-08

申请人： Micah Galland ,  Terence Hook

发明人： Micah Galland ,  Terence Hook

IPC分类号： H01L21/66

CPC分类号： H01L22/14

摘要： A process is provided for determining the effects of scattering from the edge of a resist during a doping process. Edges of a resist which has been patterned to create an n-well are simulated and individually stepped across a predetermined region in predetermined step sizes. The step sizes may vary from step to step after each step, the scattering effects due to the resist edge at its particular location is determined. A resist of virtually any shape may be divided into its component edges and each edge may be individually stepped during the process.

摘要翻译： 提供了一种用于在掺杂过程中确定来自抗蚀剂边缘的散射效应的过程。 已经图案化以形成n阱的抗蚀剂的边缘被模拟并以预定的步长单独地跨过预定区域。 步长可以在每个步骤之后逐步变化，确定由于其特定位置处的抗蚀剂边缘引起的散射效应。 实际上任何形状的抗蚀剂可以分成其部件边缘，并且每个边缘可以在该过程中单独地步进。

公开(公告)号：US20070212799A1

公开(公告)日：2007-09-13

申请号：US11749775

申请日：2007-05-17

申请人： Terence Hook ,  Jeffrey Zimmerman

发明人： Terence Hook ,  Jeffrey Zimmerman

IPC分类号： H01L21/66

CPC分类号： H01L27/0251 ,  G06F17/5045 ,  H01L21/84

摘要： Disclosed is a method for preventing charging damage in an integrated circuit design, for example, a design having silicon over insulator (SOI) transistors. The method/circuit prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source/drain and gate as susceptible devices within a given region, and connecting a element across the source/drain and the gate of each of the susceptible devices such that the element is positioned within the region. Alternatively, the method/circuit provides for connecting compensating conductors to an element to eliminate potential charging damage.

摘要翻译： 公开了一种在集成电路设计中防止充电损坏的方法，例如具有硅绝缘体（SOI）晶体管的设计。 该方法/电路通过向IC设计分配区域来防止在处理到IC器件的栅极期间的充电损坏，使得位于区域内的器件具有电独立的网络，识别可能在源极/漏极与源极/漏极之间具有电压差的器件 门作为给定区域内的敏感器件，以及将元件跨过每个敏感器件的源极/漏极和栅极连接，使得元件位于该区域内。 或者，方法/电路提供将补偿导体连接到元件以消除潜在的充电损坏。

公开(公告)号：US20060157799A1

公开(公告)日：2006-07-20

申请号：US10905682

申请日：2005-01-17

申请人： Kiran Chatty ,  Robert Gauthier ,  Terence Hook ,  Christopher Putnam ,  Mujahid Muhammad

发明人： Kiran Chatty ,  Robert Gauthier ,  Terence Hook ,  Christopher Putnam ,  Mujahid Muhammad

IPC分类号： H01L29/76

CPC分类号： H01L29/78 ,  H01L27/027

摘要： A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region of the substrate. In addition, a reduced trigger voltage region of the substrate is positioned below the drain region. The reduced trigger voltage region has a threshold voltage of about zero and comprises an undoped region of the pure wafer substrate. Thus, the reduced trigger voltage region is free of implanted N-type and P-type doping.

摘要翻译： 具有相关联的寄生横向npn双极结型晶体管的场效应晶体管包括衬底中的源极区域，与源极区域横向相邻的衬底中的沟道区域，衬底中的与沟道区域横向相邻的漏极区域，以及位于 衬底的沟道区域。 此外，衬底的降低的触发电压区域位于漏极区域的下方。 降低的触发电压区域具有约零的阈值电压，并且包括纯晶片衬底的未掺杂区域。 因此，降低的触发电压区域没有注入的N型和P型掺杂。

公开(公告)号：US20050110535A1

公开(公告)日：2005-05-26

申请号：US10707123

申请日：2003-11-21

申请人： Kerry Bernstein ,  Anthony Bonaccio ,  John Fifield ,  Allen Haar ,  Shiu Ho ,  Terence Hook ,  Michael Sorna ,  Stephen Wyatt

发明人： Kerry Bernstein ,  Anthony Bonaccio ,  John Fifield ,  Allen Haar ,  Shiu Ho ,  Terence Hook ,  Michael Sorna ,  Stephen Wyatt

IPC分类号： H03L7/06 ,  H03L7/089 ,  H03L7/093

CPC分类号： H03L7/093 ,  H03L7/0891

摘要： A circuit, including: a capacitor coupled between a first circuit node and a second circuit node and that leaks a leakage current from the first circuit node to the second circuit node; and a compensation circuit adapted to supply a compensatory current to compensate for the leakage current to the first circuit node.

摘要翻译： 一种电路，包括：电容器，耦合在第一电路节点和第二电路节点之间，并且泄漏电流从第一电路节点泄漏到第二电路节点; 以及补偿电路，其适于提供补偿电流以补偿到第一电路节点的漏电流。

公开(公告)号：US20060086984A1

公开(公告)日：2006-04-27

申请号：US11275482

申请日：2006-01-09

申请人： Terence Hook ,  Jeffery Zimmerman

发明人： Terence Hook ,  Jeffery Zimmerman

IPC分类号： H01L23/62

CPC分类号： H01L27/0251 ,  G06F17/5045 ,  H01L21/84

摘要： Disclosed is a method and circuit for preventing charging damage in an integrated circuit design, for example, a design having silicon over insulator (SOI) transistors. The method/circuit prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source/drain and gate as susceptible devices within a given region, and connecting a element across the source/drain and the gate of each of the susceptible devices such that the element is positioned within the region. Alternatively, the method/circuit provides for connecting compensating conductors to an element to eliminate potential charging damage.

摘要翻译： 公开了一种在集成电路设计中防止充电损坏的方法和电路，例如具有硅绝缘体（SOI）晶体管的设计。 该方法/电路通过向IC设计分配区域来防止在处理到IC器件的栅极期间的充电损坏，使得位于区域内的器件具有电独立的网络，识别可能在源极/漏极与源极/漏极之间具有电压差的器件 门作为给定区域内的敏感器件，以及将元件跨过每个敏感器件的源极/漏极和栅极连接，使得元件位于该区域内。 或者，方法/电路提供将补偿导体连接到元件以消除潜在的充电损坏。

公开(公告)号：US20050280097A1

公开(公告)日：2005-12-22

申请号：US10873012

申请日：2004-06-21

申请人： Brent Anderson ,  Terence Hook

发明人： Brent Anderson ,  Terence Hook

IPC分类号： H01L21/8238 ,  H01L29/76

CPC分类号： H01L21/823857

摘要： A semiconductor device and a method of fabricating the semiconductor device, the semiconductor device including: one or more FETs of a first polarity and one or more FETs of a second and opposite polarity, at least one of the one or more FETs of the first polarity having a gate dielectric having a thickness different from a thickness of a gate dielectric of at least one of the one or more FETs of the second polarity

摘要翻译： 一种半导体器件和半导体器件的制造方法，所述半导体器件包括：第一极性的一个或多个FET和具有第二极性和相反极性的一个或多个FET，所述一个或多个第一极性的FET中的至少一个 具有不同于所述第一极性的所述一个或多个FET中的至少一个的栅极电介质的厚度的栅极电介质

公开(公告)号：US20050233478A1

公开(公告)日：2005-10-20

申请号：US10709109

申请日：2004-04-14

申请人： Douglas Coolbaugh ,  Hayden Cranford ,  Terence Hook ,  Anthony Stamper

发明人： Douglas Coolbaugh ,  Hayden Cranford ,  Terence Hook ,  Anthony Stamper

IPC分类号： H01L21/00 ,  H01L23/525 ,  H01L27/08 ,  H01P3/08

CPC分类号： H01L27/0802 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.

摘要翻译： 在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。 多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个 具有高于目标值的值，并且具有低于目标值的值。 每个无源电路元件还具有与其串联的保险丝。 还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。 然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择 元素。